Semiconductor device
AssigneeUnited Microelectronics Corp.
InventorChing-Wen Hung
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.
Claims25
A semiconductor device, comprising:
- a substrate;
- a first dielectric layer on the substrate;
- a hard mask layer on the first dielectric layer;
- a trench in the hard mask layer and the first dielectric layer;
- a first source/drain electrode layer on a sidewall of the trench;
- a second dielectric layer on the first source/drain electrode layer in the trench;
- a second source/drain electrode layer on the second dielectric layer in the trench, wherein both of the first source/drain electrode layer and the second source/drain electrode layer extend along the sidewall and a bottom of the trench;
- a third dielectric layer on the second source/drain electrode layer in the trench;
- a fourth dielectric layer in the trench, dividing the second source/drain electrode layer into two portions comprising a first portion and a second portion in the trench;
- an n-type field-effect transistor (nFET) disposed over the trench;
- and
- a p-type field-effect transistor (pFET) disposed over the trench and spaced apart from the nFET, wherein the nFET and the pFET share one common gate electrode spanning the trench, wherein the nFEP and the pFET are configured to form an inverter.
A semiconductor device, comprising:
- a substrate;
- a first dielectric layer on the substrate;
- a hard mask layer on the first dielectric layer;
- a trench in the hard mask layer and the first dielectric layer;
- a first source/drain electrode layer on a sidewall of the trench;
- a second dielectric layer on the first source/drain electrode layer in the trench;
- a second source/drain electrode layer on the second dielectric layer in the trench, wherein both of the first source/drain electrode layer and the second source/drain electrode layer extend along the sidewall and a bottom of the trench;
- a third dielectric layer on the second source/drain electrode layer in the trench;
- an inter-layer dielectric (ILD) layer overlying the trench;
- an n-type field-effect transistor (nFET) disposed over the trench;
- and
- a p-type field-effect transistor (pFET) disposed over the trench and spaced apart from the nFET.
Dependencies are inferred from the claim text.