Semiconductor devices having equal thickness gate spacers
AssigneesInteranational Business Machines Corporation, Globalfoundries Inc.
InventorsCheng Chi, Ruilong Xie
Life of this patent
Estimating the term…
Abstract
A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.
Claims18
A semiconductor structure comprising:
- a p-type field effect transistor (PFET) device;
- an n-type field effect transistor (NFET) device;
- a dielectric island disposed between the PFET and NFET devices;
- a PFET sidewall spacer disposed on one side of the dielectric island;
- and
- an NFET sidewall spacer disposed on the other side of the dielectric island;
- wherein the NFET sidewall spacer has a width equal to a width of the PFET sidewall spacer, and
- wherein the dielectric island, the PFET sidewall spacer, and the NFET sidewall spacer are vertically aligned with a single common shallow trench isolation (STI) region and wherein the dielectric island directly contacts a top surface of the STI region.
A semiconductor structure comprising:
- a p-type field effect transistor (PFET) device;
- an n-type field effect transistor (NFET) device;
- a gate spacer structure separating the PFET device from the NFET device;
- and
- sidewall spacers disposed on opposed ends of the gate spacer structure,
- wherein the gate spacer structure and the sidewall spacer are vertically aligned with a single common shallow trench isolation (STI) region and wherein the gate spacer structure directly contacts a top surface of the STI region.
Dependencies are inferred from the claim text.