Silicide implants
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Yang Wu, Shiu-Ko Jang-Jian, Ting-Chun Wang, Chuan-Pu Liu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Yang Wu, Shiu-Ko Jang-Jian, Ting-Chun Wang, Chuan-Pu Liu
Estimating the term…
The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.
A method, comprising:
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Dependencies are inferred from the claim text.