Fabrication of gate all around device

A method, comprising:

• forming a gate electrode layer over a conductive layer;
• patterning the gate electrode layer into first and second gate electrodes;
• patterning the conductive layer into first and second gate pickup regions under the first and second gate electrodes, respectively;
• trimming the first and second gate electrodes to respectively expose the first and second gate pickup regions, wherein after trimming the first and second electrodes, the first and second gate electrodes have sloped sidewalls respectively extending from exposed top surfaces of the first and second gate pickup regions at an obtuse angle;
• and
• after trimming the first and second gate electrodes, forming first and second gate contacts respectively over the first and second gate pickup regions.

A method, comprising:

• forming in sequence a conductive layer, a dielectric layer and a gate electrode layer over a substrate;
• patterning the gate electrode layer to form a gate electrode over the dielectric layer, the gate electrode having a horizontal dimension decreasing as a distance from the dielectric layer increases;
• patterning the dielectric layer and the conductive layer to form a patterned dielectric layer under the gate electrode and a source/drain pickup region under the patterned dielectric layer, the source/drain pickup region having a horizontal dimension increasing as a distance from the gate electrode increases;
• etching a top surface of the gate electrode until exposing the source/drain pickup region;
• after etching the top surface of the gate electrode, forming a gate dielectric layer lining an inner sidewall of the gate electrode;
• and
• forming a nanowire surrounded by the gate dielectric layer.