# US 10,763,336 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 10,763,336 B2
- Document ID: US10763336B2
- Status: Granted
- Kind: B2
- Application number: 16/121,346
- Filed: 2018-09-04
- Published: 2019-03-28
- Granted: 2020-09-01
- Earliest claimed: 2017-09-28
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Hiroshi Yanagigawa
- Web page: https://patentgrep.com/patent/US10763336B2

## CPC

- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H02H 7/18: for batteries; for accumulators
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device. A first MOS transistor and a second MOS transistor configure a bidirectional switch. The first MOS transistor and second MOS transistor each have a vertical trench structure. A first impurity region abuts on the side wall of a first gate trench of a first MOS transistor element outside the first MOS transistor area and is electrically coupled to a first source region.

## Claims

### Claim 1

A semiconductor device having a bidirectional switch, the semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface opposite to each other and having a first gate trench extending from the first surface toward the second surface;
a first transistor element which includes a first drain region of a first conductivity type located in the second surface, a first source region of the first conductivity type located in the first surface, and a first gate electrode located inside the first gate trench and is included in the bidirectional switch;
a first impurity region of a second conductivity type which abuts on a side wall of the first gate trench outside an area for the first transistor element and is electrically coupled to the first source region; and
a first base region of the second conductivity type making a PN junction with the first source region and facing the first gate electrode while being insulated therefrom,
wherein the first impurity region has a larger depth from the first surface than the first base region and has a lower impurity concentration than the first base region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the semiconductor substrate has a second gate trench extending from the first surface toward the second surface,
wherein the semiconductor device further comprises:
a second transistor element which includes a second drain region of the first conductivity type located in the second surface, a second source region of the first conductivity type located in the first surface, and a second gate electrode located inside the second gate trench and is included in the bidirectional switch; and
a second impurity region of the second conductivity type which abuts on a side wall of the second gate trench outside an area for the second transistor element and is electrically coupled to the second source region.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the first impurity region and the second impurity region are separated from each other.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a source electrode located over the first surface;
a first conductive layer coupled to the source electrode and the first source region; and
a second conductive layer coupled to the source electrode and the first impurity region,
wherein the first conductive layer extends into the semiconductor substrate from the first surface deeper than the second conductive layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a gate insulating layer located between a wall face of the first gate trench and the first gate electrode,
wherein the gate insulating layer has a first thickness in a first region from the first surface to a first depth and has a second thickness larger than the first thickness in a second region from the first depth to a second depth nearer to the second surface, and
wherein the first impurity region extends from the first surface to a depth position nearer to the second surface than the first depth.

### Claim 6 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a second base region of the second conductivity type making a PN junction with the second source region and facing the second gate electrode while being insulated therefrom;
a first column region of the second conductivity type being coupled to the first base region and extending from the first base region toward the second surface; and
a second column region of the second conductivity type being coupled to the second base region and extending from the second base region toward the second surface.

### Claim 7 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a second base region of the second conductivity type making a PN junction with the second source region and facing the second gate electrode while being insulated therefrom;
an epitaxial region of the first conductivity type making a PN junction with each of the first base region and the second base region; and
a column region of the second conductivity type which is located in the epitaxial region between the area for the first transistor element and the area for the second transistor element and has a floating potential.

### Claim 8 (depends on 2)

The semiconductor device according to claim 2, wherein the second impurity region has a larger depth from the first surface than the second base region and has a lower impurity concentration than the second base region.