Image sensor chips having sub-chips

An image sensor chip, comprising:

• a first sub-chip;
• a second sub-chip on the first sub-chip;
• and
• an interconnector between the first and second sub-chips,
• wherein the first sub-chip comprises:
• a first substrate including a first region and a second region;
• and
• first and second capacitors provided respectively on the first and second regions,
• wherein the second sub-chip comprises a pixel array that is configured to convert incident light into an electrical signal,
• wherein the first capacitor is electrically connected to a memory transistor on the first region,
• wherein the second capacitor is electrically connected through the interconnector to the pixel array,
• wherein each of the first and second capacitors comprises:
• a plurality of first electrodes extending in a direction perpendicular to a top surface of the first substrate;
• a second electrode on the first electrodes;
• and
• a dielectric layer between the second electrode and the first electrodes,
• wherein the memory transistor comprises:
• an active region on the first region and including a first impurity region and a second impurity region;
• a gate line between the first and second impurity regions and embedded in the active region, and
• a bit line electrically connected to the first impurity region, and
• wherein the first capacitor is electrically connected to the second impurity region.

An image sensor chip, comprising:

• a first sub-chip comprising a memory cell zone and a signal processing zone;
• a second sub-chip on the first sub-chip, the second sub-chip comprising a pixel array configured to convert incident light into an electrical signal;
• and
• a third sub-chip on a bottom surface of the first sub-chip opposite the second sub-chip, the third sub-chip comprises a logic zone,
• wherein the first sub-chip comprises:
• a first capacitor on the memory cell zone;
• and
• a second capacitor on the signal processing zone,
• wherein each of the first and second capacitors comprises a plurality of vertically extending first electrodes,
• wherein top surfaces of the first electrodes of the first capacitor are substantially coplanar with top surfaces of the first electrodes of the second capacitor.