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US 10,763,292 B2Granted
Interconnect apparatus and method for a stacked semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih-Pei Chou, Min-Feng Kao, Szu-Ying Chen
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Abstract
A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.
Claims20
A method comprising:
- bonding a first semiconductor chip on a second semiconductor chip;
- depositing a first hard mask layer over the first semiconductor chip, wherein the first hard mask layer comprises polysilicon;
- depositing a second hard mask layer over the first hard mask layer, wherein the second hard mask layer comprises an oxide;
- performing a first etching process and a second etching process on the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, the first etching process using the second hard mask layer as a mask and the second etching process using the first hard mask layer as a mask, wherein as a result of performing the first and the second etching process, an opening is formed in the first semiconductor chip, wherein the opening includes a first portion extending into a metal element of the first semiconductor chip and a second portion over the metal element;
- and
- plating a conductive material in the opening to from a conductive plug.
3 more elements
A method comprising:
- bonding a first semiconductor chip on a second semiconductor chip, wherein the first semiconductor chip includes a substrate and a plurality of inter-metal dielectric layers;
- depositing a first hard mask layer over the first semiconductor chip, wherein the first hard mask layer comprises polysilicon;
- depositing a second hard mask layer over the first hard mask layer, wherein the second hard mask layer comprises an oxide;
- etching a first opening through the substrate using the second hard mask layer as a mask;
- etching a second opening partially through the plurality of inter-metal dielectric layers using the first hard mask layer as a mask, wherein after etching the second opening, a metal surface of a conductive element of the first semiconductor chip is exposed;
- etching the first semiconductor chip and the second semiconductor chip to form a third opening extending through the first semiconductor chip and partially through the second semiconductor chip, a portion of the third opening being surrounded by the conductive element of the first semiconductor chip, wherein after forming the third opening a metal surface of the second semiconductor chip is exposed, wherein a portion of the second opening extends into the conductive element of the first semiconductor chip;
- and
- plating a conductive material in the first, second, and third openings to from a conductive plug.
5 more elements
A method comprising:
- bonding a first semiconductor chip on a second semiconductor chip;
- depositing a first hard mask layer over the first semiconductor chip, wherein the first hard mask layer comprises polysilicon;
- depositing a second hard mask layer over the first hard mask layer, wherein the second hard mask layer comprises an oxide;
- performing a first and a second etching process on the first semiconductor chip until an interconnect element of the first semiconductor chip is exposed, the first etching process using the second hard mask layer as a mask and the second etching process using the first hard mask layer as a mask, wherein as a result of performing the first and second etching process, a first opening is formed in the first semiconductor chip;
- performing a third etching process on the first semiconductor chip and the second semiconductor chip until an interconnect element of the second semiconductor chip is exposed, the third etching process using the interconnect element of the first semiconductor chip as a mask, the third etching process resulting in a second opening being formed in the first semiconductor chip and the second semiconductor chip, wherein a portion of the first opening extends into the interconnect element of the first semiconductor chip;
- and
- plating a conductive material in the first and second openings to from a conductive plug.
4 more elements
Dependencies are inferred from the claim text.