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US 10,763,278 B2Granted
Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsKyunghwa Yun, Pansuk Kwak, Chanho Kim, Junghwa Lee
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Abstract
A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.
Claims20
A semiconductor memory device, comprising:
- a substrate having a cell array region and a contact region;
- a stack structure on the cell array region and the contact region of the substrate and comprising a plurality of gate electrodes, the gate electrodes being disposed one over another in the stack structure;
- a plurality of cell vertical channel structures on the cell array region of the substrate and extending through the stack structure;
- and
- a contact structure disposed beside the stack structure on a top surface of the substrate and disposed on both the cell array region and the contact region of the substrate along a line extending from the cell array region onto the contact region,
- wherein the contact structure is connected to a common source region disposed in the substrate, has a first height on the cell array region and a second height on the contact region, and the first height is different than the second height.
3 more elements
A semiconductor memory device, comprising:
- a substrate having a cell array region and a contact region;
- a stack structure on the cell array region and the contact region of the substrate and comprising a plurality of gate electrodes, the gate electrodes being disposed one over another in the stack structure;
- a plurality of cell vertical channel structures extending through the stack structure on the cell array region of the substrate;
- a contact structure disposed beside the stack structure on a top surface of the substrate and disposed on both the cell array region and the contact region of the substrate along a line extending from the cell array region onto the contact region;
- and
- an interlayer dielectric structure covering a top surface of the contact structure,
- wherein the interlayer dielectric structure has a first thickness on the cell array region and a second thickness on the contact region, and
- the first thickness of the interlayer dielectric structure is different from the second thickness of the interlayer dielectric structure.
5 more elements
A semiconductor memory device, comprising:
- a substrate having a cell array region, a contact region and a peripheral region;
- a peripheral transistor located at an upper portion of the peripheral region of the substrate;
- a stack structure on the cell array region and the contact region of the substrate and comprising a plurality of gate electrodes, the gate electrodes being disposed one over another in the stack structure, and the plurality of gate electrodes having a staircase-shaped portion on the contact region;
- a plurality of cell vertical channel structures extending through the stack structure on the cell array region of the substrate;
- a contact structure disposed beside the stack structure on a top surface of the substrate and disposed on the cell array region and the contact region of the substrate along a line extending from the cell array region onto the contact region, the contact structure having a top surface including a first portion on the contact region of the substrate and a second portion on the cell array region, the first portion of the top surface of the contact structure being situated at a level lower than that of the second portion of the top surface of the contact structure;
- an interlayer dielectric layer extending over the contact structure, over the stack structure on the cell array region and the contact region of the substrate, and over the peripheral transistor on the peripheral region of the substrate, the interlayer dielectric layer having a step such that a first portion of a top surface of the interlayer dielectric layer on the peripheral region of the substrate is situated at a level lower than that of a second portion of the top surface of the interlayer dielectric layer on the cell array region of the substrate;
- a first cell contact plug on an end of a first one of the gate electrodes that is disposed on the contact region of the substrate, the first cell contact plug having a top surface at a same level as the first portion of the top surface of the interlayer dielectric layer;
- a second cell contact plug on an end of a second one of the gate electrodes that is disposed on the contact region of the substrate, the second cell contact plug being disposed closer to the cell array region than the first cell contact plug;
- a first connection line extending along the first portion of the top surface of the interlayer dielectric layer from the top surface of the first cell contact plug and over the peripheral region of the substrate, the first connection line being electrically connected to the peripheral transistor;
- and
- a second connection line situated at a level above that of the first connection line,
- wherein the second connection line is electrically connected to the second cell contact plug at a location situated at a same level as or at a level above the second portion of the top surface of the interlayer dielectric layer.
9 more elements
Dependencies are inferred from the claim text.