# US 10,763,277 B2 · Semiconductor memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,763,277 B2
- Document ID: US10763277B2
- Status: Granted
- Kind: B2
- Application number: 16/118,598
- Filed: 2018-08-31
- Published: 2019-09-19
- Granted: 2020-09-01
- Earliest claimed: 2018-03-14
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Go Oike; Tsuyoshi Sugisaki
- Web page: https://patentgrep.com/patent/US10763277B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

## Claims

### Claim 1

A semiconductor memory device comprising:
a plurality of first interconnect layers stacked in a first direction;
first and second memory pillars extending in the plurality of first interconnect layers; and
a plurality of first plugs respectively contacting the plurality of first interconnect layers,
wherein the plurality of first interconnect layers include:
a first region where the first memory pillar extends in the plurality of first interconnect layers;
a second region where the second memory pillar extends in the plurality of first interconnect layers; and
a third region where the plurality of first plugs are respectively contacted to one of the plurality of first interconnect layers, and
the first region, the third region, and the second region are arranged in order along a second direction crossing the first direction.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the third region includes a plurality of coupling parts which are respectively coupled to the one of the plurality of first interconnect layers, and
the plurality of coupling parts are arranged stepwise along the second direction.

### Claim 3 (depends on 2)

The device according to claim 2, wherein at least a part of the plurality of coupling parts is arranged in a two-stage stepwise shape.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the plurality of coupling parts are arranged in a two-row stepwise shape along the first direction.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising a plurality of second plugs which extend in the plurality of first interconnect layers, upper surfaces of which are electrically coupled to the plurality of first plugs respectively, and which are provided in the third region.

### Claim 6 (depends on 1)

The device according to claim 1, wherein a first interconnect layer positioned in an uppermost layer among the plurality of first interconnect layers includes a first interconnect part contacting the first memory pillar and a second interconnect part contacting the second memory pillar, which are separated in the third region.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the first and second memory pillars each includes a semiconductor layer, and a second insulating layer, a charge storage layer, and a third insulating layer, which are provided in order on a side surface of the semiconductor layer.

### Claim 8 (depends on 5)

The device according to claim 5, further comprising a circuit which is provided below the plurality of first interconnect layers and to which bottom surfaces of the plurality of second plugs are electrically coupled.

### Claim 9 (depends on 8)

The device according to claim 8, wherein the circuit is a row decoder.

### Claim 10 (depends on 7)

The device according to claim 7, further comprising a second interconnect layer provided above the first memory pillar and electrically coupled to the semiconductor layer of the first memory pillar.

### Claim 11 (depends on 10)

The device according to claim 10, further comprising a sense amplifier to which the second interconnect layer is coupled.

### Claim 12 (depends on 1)

The device according to claim 1, further comprising a third interconnect layer provided below the plurality of first interconnect layers and contacting bottom surfaces of the first and second pillars.

### Claim 13 (depends on 1)

The device according to claim 1, wherein end portions of the plurality of first interconnect layers are arranged stepwise along the second direction.

### Claim 14 (depends on 1)

The device according to claim 1, further comprising:
a third memory pillar provided in the first region; and
a fourth memory pillar provided in the second region,
wherein a first interconnect layer positioned in an uppermost layer among the plurality of first interconnect layers includes:
a first interconnect part extending in the second direction and contacting a side surface of the first memory pillar in the first region;
a second interconnect part adjacent to the first interconnect part, extending in the second direction, and contacting a side surface of the third memory pillar in the first region;
a third interconnect part extending in the second direction and contacting a side surface of the second memory pillar in the second region; and
a fourth interconnect part adjacent to the third interconnect part, extending in the second direction, and contacting a side surface of the fourth memory pillar in the second region.

### Claim 15 (depends on 14)

The device according to claim 14, wherein different first plugs among the plurality of first plugs are respectively coupled to the first-to-fourth interconnect parts.

### Claim 16 (depends on 3)

The device according to claim 3, wherein the plurality of coupling parts of even-numbered steps and the plurality of coupling parts of odd-numbered steps are respectively arranged in the two-stage stepwise shape.

### Claim 17 (depends on 16)

The device according to claim 16, wherein the plurality of coupling parts of the even-numbered steps are arranged by two steps from one end of the third region toward a center of the third region along the second direction, and the plurality of coupling parts of the odd-numbered steps are arranged by the two steps from another end of the coupling region toward the center along the second direction.