3D NAND device

A 3D NAND device, comprising:

• a semiconductor substrate having a first region and at least one second region;
• multi-layer stacked memory structures formed on the semiconductor substrate in the first region;
• a control gate structure having a plurality of staircase-stacked layers from a bottom layer to a top layer formed on the semiconductor substrate, each layer of the control gate structure having a first end electrically connected with a corresponding layer of memory structures, each layer of the control gate structure has an insulation layer and a conductive layer formed on the insulation layer, and a second end opposing to the first end, wherein the bottom layer is formed directly on the semiconductor substrate;
• a dielectric layer covering a top surface of the top layer, the control gate structure, the memory structures, and the semiconductor substrate;
• and
• a metal via formed directly on a corresponding surface of second end of each conductive layer of the control gate structure and electrically connected with the second end of the conductive layer of each of the plurality of layers of the control gate structure, wherein the metal vias are formed by:
• forming a hard mask layer on the dielectric layer;
• patterning the hard mask layer to form a plurality of openings above corresponding second ends of the plurality of layers of the control gate structure;
• forming a photoresist layer on the hard mask layer and in the plurality of openings;
• repeating a photoresist trimming process and a first etching process to sequentially expose the plurality of openings, and to form a plurality of holes with predetermined depths in the dielectric layer above the corresponding second ends, wherein a bottom of each of the plurality of holes has a same distance respective to the corresponding surface of second end of each conductive layer of the control gate structure;
• performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes, wherein performing the second etching process to etch each of the plurality of holes until surfaces of the second ends are exposed has a same time duration;
• and forming a metal via in etch of the plurality of through holes.