Vertical GAA flash memory including two-transistor memory cells

A method of manufacturing a memory device, comprising:

• forming an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor, including:
• forming a plurality of stacks of conductive lines separated by insulating layers on a reference line on a substrate, a stack of conductive lines in the plurality of stacks including a select gate line and a word line adjacent the select gate line;
• forming an array of vertical channel lines disposed through the conductive lines in the plurality of stacks to the reference line;
• forming gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors located at cross-points of the array of vertical channel lines and the select gate line;
• forming charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors located at cross-points of the array of vertical channel lines and the word line;
• and
• forming a plurality of bit lines overlying the array of vertical channel lines coupled to the vertical channel lines via upper ends of the vertical channel lines,
• wherein one of the select gate line and the word line adjacent the select gate line is adjacent the reference line, and another of the select gate line and the word line adjacent the select gate line is adjacent a bit line in the plurality of bit lines.

A memory device, comprising:

• a two-transistor memory cell including a vertical select transistor having a first channel region in a vertical semiconductor pillar and a vertical data storage transistor having a second channel region in the vertical semiconductor pillar;
• the vertical semiconductor pillar having a top region) above the first channel region acting as a first current conducting terminal of the vertical select transistor, a bottom region below the second channel region acting as a second current conducting terminal of the vertical data storage transistor, and an intermediate region between the first channel region and the second channel region acting as a second current conducting terminal of the vertical select transistor and a first current conducting terminal of the vertical data storage transistor;
• a bit line coupled to the top region of the vertical semiconductor pillar;
• and
• a reference line coupled to the bottom region of the vertical semiconductor pillar;
• a select gate line surrounding the first channel region in the vertical semiconductor pillar;
• a gate dielectric structure disposed between the select gate line and the first channel region in the vertical semiconductor pillar;
• a word line surrounding the second channel region in the vertical semiconductor pillar;
• and
• a charge storage structure disposed between the word line and the second channel region in the vertical semiconductor pillar,
• wherein the word line is adjacent the select gate line, and one of the select gate line and the word line adjacent the select gate line is adjacent the reference line, and another of the select gate line and the word line adjacent the select gate line is adjacent the bit line.