Method for forming an integrated circuit and an integrated circuit

A method for forming an integrated circuit (IC), the method comprising:

• recessing a memory region of a substrate relative to a logic region of the substrate;
• forming an isolation structure separating the memory region from the logic region;
• performing a first etch into the isolation structure to form a memory sidewall facing the memory region and slanting downward toward the memory region;
• forming a memory cell structure on the memory region;
• forming a capping layer covering the memory cell structure, the logic region, and the isolation structure;
• performing a second etch into the capping layer to remove the capping layer from the logic region, wherein the second etch forms a logic sidewall from the capping layer, and wherein the logic sidewall is slanted downward towards the logic region;
• recessing a first top surface portion of the isolation structure relative to a second top surface portion of the isolation structure, wherein the recessing of the first top surface portion extends the logic sidewall downward from the second top surface portion to the first top surface portion, and wherein the second top surface portion extends from the memory sidewall to the logic sidewall;
• forming a logic device structure on the logic region while the capping layer covers the memory region and after the recessing of the first top surface portion;
• and
• performing a third etch into the capping layer to remove the capping layer from the memory region and the memory sidewall, while leaving a dummy segment of the capping layer on the second top surface portion of the isolation structure, wherein the dummy segment and the isolation structure at least partially define the logic sidewall.

A method for forming an integrated circuit (IC), the method comprising:

• forming an isolation structure separating a memory region of a substrate from a logic region of the substrate;
• forming a memory cell structure on the memory region;
• forming a capping layer covering the memory cell structure, the isolation structure, and the logic region, wherein the forming of the capping layer comprises depositing the capping layer and performing a planarization into the capping layer to flatten a top surface of the capping layer, wherein the top surface slants downward from the logic region to the memory region upon completion of the planarization;
• patterning the capping layer to remove the capping layer from the logic region, but not the memory region, and to further form a logic sidewall facing the logic region and slanting downward towards the logic region;
• forming a multilayer film overlying the capping layer and covering the memory region, the logic region, and the isolation structure;
• performing a first etch into the multilayer film to concurrently form a device structure and a dummy structure respectively on the logic region and the isolation structure;
• and
• removing the capping layer from the memory region.