Memory structure with multi-cell poly pitch
AssigneeArm Limited
InventorsYew Keong Chong, Sriram Thyagarajan, Munish Kumar
Life of this patent
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Abstract
Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
Claims19
An integrated circuit, comprising:
- a memory structure having a two-bitcell layout with a four cell poly pitch,
- wherein the two-bitcell layout includes a first bitcell and a second bitcell having structural contours that are joined together in a coupling arrangement, and
- wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations.
An integrated circuit, comprising:
- a memory structure having a two-bitcell layout in a coupling arrangement,
- wherein the two-bitcell layout includes a first bitcell and a second bitcell having non-linear structural contours that are joined together in the coupling arrangement, and
- wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations, wherein the non-linear structural contours refer to L-shaped structural contours that are joined together in a reciprocal arrangement.
An integrated circuit, comprising:
- a memory structure having a two-bitcell layout in a coupling arrangement,
- wherein the two-bitcell layout includes a first bitcell and a second bitcell having structural contours that are joined together in the coupling arrangement, and wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations, wherein the memory structure comprises a multi-port memory structure.
An integrated circuit, comprising:
- a memory structure having a two-bitcell layout in a coupling arrangement,
- wherein the two-bitcell layout includes a first bitcell and a second bitcell having structural contours that are joined together in the coupling arrangement, and wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations, wherein the first bitcell and the second bitcell are eight transistor (8T) bitcells.
A method, comprising:
- fabricating a memory structure having a two-bitcell layout with a four cell poly pitch;
- fabricating the two-bitcell layout with a first bitcell and a second bitcell having structural contours that are joined together in a coupling arrangement;
- and
- fabricating the first bitcell and the second bitcell with multiple transistors arranged to store data during write operations and allow access of data during read operations.
Dependencies are inferred from the claim text.