Semiconductor device manufacturing method

A semiconductor device manufacturing method, comprising:

• providing a semiconductor structure, comprising:
• a substrate;
• a plurality of semiconductor fins on the substrate;
• a plurality of trenches surrounding the semiconductor fins;
• and a first insulation layer filling the trenches, wherein the plurality of semiconductor fins comprises a first semiconductor fin for a first device and a second semiconductor fin for a second device;
• conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein;
• removing at least a portion of the first insulation layer so that at least a portion of the trenches is no longer filled by the first insulation layer;
• forming a second insulation layer filling the portion of the trenches not filled by the first insulation layer;
• and
• conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein,
• wherein the first doping process is a first ion implantation, and the second doping process is a second ion implantation,
• wherein the first device is an N-type Metal-Oxide-Semiconductor (NMOS) device, and the second device is a P-type Metal-Oxide-Semiconductor (PMOS) device,
• wherein the conditions under which the first ion implantation is conducted include:
• an implanted ion is a P-type dopant, an implantation energy is in a range of 10 keV to 20 keV, and an implantation dose is in a range of 1.0×1013 atom/cm2 to 4.0×1014 atom/cm2, and
• wherein the conditions under which the second ion implantation is conducted include:
• an implanted ion is an N-type dopant, an implantation energy is in a range of 35 keV to 120 keV, and an implantation dose is in a range of 1.0×1013 atom/cm2 to 5.0×1014 atom/cm2.

A semiconductor device manufacturing method, comprising:

• providing a semiconductor structure, comprising:
• a substrate;
• a plurality of semiconductor fins on the substrate;
• a plurality of trenches surrounding the semiconductor fins;
• and a first insulation layer filling the trenches, wherein the plurality of semiconductor fins comprises a first semiconductor fin for a first device and a second semiconductor fin for a second device;
• conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein;
• removing at least a portion of the first insulation layer so that at least a portion of the trenches is no longer filled by the first insulation layer;
• forming a second insulation layer filling the portion of the trenches not filled by the first insulation layer;
• and
• conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein,
• wherein in providing the semiconductor structure, the semiconductor structure further comprises:
• a hard mask layer on the semiconductor fins, wherein an upper surface of the first insulation layer is on the same horizontal level with an upper surface of the hard mask layer, and wherein the first doping process is conducted in the first semiconductor find through the hard mask layer,
• wherein conducting the first doping process in the first semiconductor fin through the hard mask layer comprises:
• forming a patterned first mask layer on the semiconductor structure after the first insulation is formed, wherein the first mask layer exposes a portion of the hard mask layer on the first semiconductor fin;
• through the exposed portion of the hard mask layer, conducting the first doping process in the first semiconductor fin to form a first anti-punch-through region in the first semiconductor fin;
• and removing the first mask layer.