US 10,763,258 B2Granted

Integrated circuit and manufacturing method thereof

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChe-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng

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Abstract

An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

Claims20

Dependent claims

A method for manufacturing an integrated circuit, the method comprising:

forming a gate layer on a substrate, the gate layer having a first portion and a second portion;
doping the first portion of the gate layer with first dopants while leaving the second portion of the gate layer undoped with the first dopants;
doping the second portion of the gate layer with second dopants, wherein the first dopants have a first composition and the second dopants have a second composition different than the first composition;
patterning the first portion of the gate layer to form a first gate structure and patterning the second portion of the gate layer to form a second gate structure, wherein:
an etch profile for the first portion of the gate layer is different than an etch profile for the second portion of the gate layer due to the first composition being different than the second composition such that a first cross-sectional profile of the first gate structure is different than a second cross-sectional profile of the second gate structure;
forming a first spacer and a second spacer, wherein the first gate structure is disposed between the first spacer and the second spacer;
removing the first gate structure to define a first opening between the first spacer and the second spacer;
and
forming a first metal gate structure in the first opening.

6 more elements

A method for manufacturing an integrated circuit, comprising:

forming a gate layer over a substrate;
forming a first mask over a first portion of the gate layer and doping a second portion of the gate layer that is not masked by the first mask using first dopants;
removing the first mask;
forming a second mask over the second portion of the gate layer and doping the first portion of the gate layer that is not masked by the second mask using second dopants, wherein the first dopants have a first composition and the second dopants have a second composition different than the first composition;
and
patterning the first portion of the gate layer to form a first gate structure and patterning the second portion of the gate layer to form a second gate structure, wherein:
an etch profile for the first portion of the gate layer is different than an etch profile for the second portion of the gate layer due to the first composition being different than the second composition such the first gate structure has a first cross-sectional profile and the second gate structure has a second cross-sectional profile different than the first cross-sectional profile, and
at least one of the first cross-sectional profile or the second cross-sectional profile comprises:
a tapered portion, and
a non-tapered portion.

7 more elements

A method for manufacturing an integrated circuit, comprising:

forming a gate layer on a substrate, the gate layer having a first portion and a second portion;
doping the first portion of the gate layer with first dopants while leaving the second portion of the gate layer undoped with the first dopants;
doping the second portion of the gate layer with second dopants, wherein the first dopants have a first composition and the second dopants have a second composition different than the first composition;
patterning the first portion of the gate layer to form a first gate structure;
patterning the second portion of the gate layer to form a second gate structure, wherein:
an etch profile for the first portion of the gate layer is different than an etch profile for the second portion of the gate layer due to the first composition being different than the second composition such that a first cross-sectional profile of the first gate structure is different than a second cross-sectional profile of the second gate structure:
forming a first epitaxial region adjacent a first sidewall of the first gate structure;
and
forming a second epitaxial region adjacent a second sidewall of the second gate structure.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/990,807Filed 28 May 2018 · division
Priority: 21 Jan 2016
Published: US 2018/0277544 A127 Sep 2018
Granted: 1 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 84/853
Complementary IGFETs, e.g. CMOS: comprising FinFETs
H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
H10D 64/01324
Characterised by the conductor: characterised by the sectional shape, e.g. T or inverted-T
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Family

Application62/281,459Us provisional application · filed 21 Jan 2016
Application15/074,985Parent of this division · filed 18 Mar 2016
US 2018/0277544 A1Pre-grant publication · published 27 Sep 2018
US 9,985,031 B2Parent of this division
US 2017/0213828 A1Published application
US 10,763,258 B2This patent

From the US filing history. Foreign family members aren’t listed.