Back to results
US 10,763,255 B2Granted
Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang
Life of this patent
Estimating the term…
Abstract
A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.
Claims20
A semiconductor device, comprising:
- a first fin;
- a second fin;
- an isolation structure between the first fin and the second fin;
- a dielectric stage in the isolation structure;
- and
- a helmet layer over the dielectric stage and having a first portion, a second portion, and a third portion connecting the first and second portions, wherein a top surface of the helmet layer is higher than a top surface of the isolation structure, and each of the first and second portions of the helmet layer is thicker than the third portion of the helmet layer.
3 more elements
A semiconductor device, comprising:
- a first fin;
- a second fin;
- a dielectric stage between an end surface of the first fin and an end surface of the second fin;
- a dielectric dummy fin layer wrapping around the dielectric stage and in contact with the end surface of the first fin;
- and
- a helmet layer over the dielectric stage.
3 more elements
A semiconductor device, comprising:
- a substrate;
- a first semiconductor fin extending upward from the substrate;
- a second semiconductor fin extending upward from the substrate;
- a gate structure across the first and second semiconductor fins;
- a first dielectric layer interposed between the first and second semiconductor fins and has a U-shape when viewed in a cross section taken along a lengthwise direction of the gate structure;
- a second dielectric layer capped by the first dielectric layer;
- and
- an etch stop layer extending above the first semiconductor fin and along a top surface of the first dielectric layer and a top surface of second dielectric layer, wherein a first portion of the etch stop layer in contact with the first dielectric layer is higher than a second portion of the etch stop layer in contact with the second dielectric layer.
5 more elements
Dependencies are inferred from the claim text.