Semiconductor device

A semiconductor device, comprising:

• a substrate including a first region and a second region;
• a first gate structure and a second gate structure on the substrate of the first region, the first gate structure and the second gate structure being spaced apart by a first distance;
• a third gate structure and a fourth gate structure on the substrate of the second region, the third gate structure and the fourth gate structure being spaced apart by a second distance different from the first distance;
• a first interlayer insulating film on the substrate of the first region, the first interlayer insulating film including a first lower interlayer insulating film and a first upper interlayer insulating film on the first lower interlayer insulating film, the first lower interlayer insulating film surrounding a portion of a sidewall of the first gate structure and a portion of a sidewall of the second gate structure, an upper surface of the first lower interlayer insulating film being lower than an upper surface of the first gate structure;
• a second interlayer insulating film on the substrate of the second region, the second interlayer insulating film including a second lower interlayer insulating film and a second upper interlayer insulating film on the second lower interlayer insulating film, the second lower interlayer insulating film surrounding a portion of a sidewall of the third gate structure and a portion of a sidewall of the fourth gate structure, an upper surface of the second lower interlayer insulating film being lower than an upper surface of the third gate structure;
• a first contact between the first gate structure and the second gate structure, the first contact being within the first interlayer insulating film and having a first width;
• a second contact between the third gate structure and the fourth gate structure, the second contact being within the second interlayer insulating film and having a second width different from the first width;
• and
• a first fin-type pattern and a second fin-type pattern protruding from the substrate,
• the first gate structure and the second gate structure intersecting the first fin-type pattern,
• the third gate structure and the fourth gate structure intersecting the second fin-type pattern,
• wherein the first width being correlated to a width of the upper surface of the first gate structure, and the second width being correlated to a width of the upper surface of the third gate structure, and
• wherein the first gate structure includes a gate spacer defining a trench, a gate insulating film along a sidewall and a bottom surface of the trench, and a gate electrode on the gate insulating film and filling the trench.