# US 10,763,248 B2 · Multi-layer silicon/gallium nitride semiconductor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,763,248 B2 - Document ID: US10763248B2 - Status: Granted - Kind: B2 - Application number: 15/754,822 - Filed: 2015-09-24 - Published: 2020-07-16 - Granted: 2020-09-01 - Earliest claimed: 2015-09-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Sansaptak W. Dasgupta; Marko Radosavljevic; Han Wui Then; Ravi Pillarisetty; Kimin Jun; Patrick Morrow; Valluri R. Rao; Paul B. Fischer; Robert S. Chau - Web page: https://patentgrep.com/patent/US10763248B2 ## CPC - H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies - H10W 90/00: Package configurations - H10D 88/00: Three-dimensional [3D] integrated devices - H10P 95/11: {Separation of active layers from substrates} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/07331: {Connecting techniques} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 90/20: Configurations of stacked chips - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/732: {between stacked chips} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced. ## Claims ### Claim 1 A compound semiconductor device; comprising: a completed silicon layer that includes a number of silicon dies, each of the silicon dies including at least one silicon integrated circuit; a completed gallium nitride (GaN) layer that includes a number of GaN dies, each of the GaN dies including at least one GaN integrated circuit, the completed GaN layer bonded, via layer transfer, to the completed silicon layer such that each of the number of silicon dies lies proximate a respective one of the number of GaN dies; and an interconnect layer deposited on the completed GaN layer, the interconnect layer including a number of thru-GaN vias that conductively couple the at least one GaN integrated circuit on each GaN die with the at least one silicon integrated circuit on each silicon die. ### Claim 2 (depends on 1) The compound semiconductor device of claim 1 wherein the GaN dies have a defined polarization. ### Claim 3 (depends on 2) The compound semiconductor device of claim 2 wherein the defined polarization vector is directed from the channel to the gate of the at least one GaN integrated circuit. ### Claim 4 (depends on 1) The compound semiconductor device of any of claim 1 wherein the at least one GaN integrated circuit comprises a power management integrated circuit (PMIC) and the at least one silicon integrated circuit comprises a complementary metal oxide semiconductor (CMOS) PMIC controller. ### Claim 5 A compound semiconductor, comprising a completed silicon layer that includes a number of silicon dies; a completed gallium nitride (GaN) layer that includes a number of GaN dies, the completed GaN layer bonded, via layer transfer, to the completed silicon layer such that each of the number of silicon dies lies proximate a respective one of the number of GaN dies; and a number of interconnections conductively coupling each of the number of silicon dies to a respective one of the GaN die to provide a multi-layer semiconductor package. ### Claim 6 (depends on 5) The multilayer semiconductor of claim 5 wherein the GaN dies have a defined polarization. ### Claim 7 (depends on 6) The multilayer semiconductor of claim 6 wherein the GaN dies include one or more GaN semiconductor devices; and wherein the defined polarization of each of the GaN semiconductor devices extends from the channel to the gate of the respective GaN semiconductor device. ### Claim 8 (depends on 5) The multilayer semiconductor of claim 5 wherein the number of interconnections comprises an interconnect layer patterned onto the completed GaN layer. ### Claim 9 A method of forming a compound semiconductor, the method comprising: bonding a completed gallium nitride (GaN) layer having a first diameter and including a number of completed GaN dies to a completed silicon layer having a second diameter and including a number of completed silicon dies; and conductively coupling at least one integrated circuit on each of the number of GaN dies to at least one integrated circuit on each of the completed silicon dies. ### Claim 10 (depends on 9) The method of claim 9 wherein bonding a completed gallium nitride (GaN) layer to a completed silicon layer comprises: layer transferring the completed GaN layer to the completed silicon layer. ### Claim 11 (depends on 9) The method of claim 9 wherein bonding a completed gallium nitride (GaN) layer having a first diameter and including a number of completed GaN dies to a completed silicon layer having a second diameter comprises: bonding a completed gallium nitride (GaN) layer having a first diameter and including a number of completed GaN dies to a completed silicon layer having a second diameter approximately equal to the first diameter. ### Claim 12 (depends on 9) The method of claim 9, further comprising: growing a GaN wafer on a silicon substrate; disposing a number of devices in, on, or about the GaN wafer; and patterning a number of conductors on the GaN wafer to conductively couple at least some of the number of devices to provide the completed GaN layer. ### Claim 13 (depends on 12) The method of claim 12 wherein growing a GaN wafer on a silicon substrate comprises: growing a GaN wafer on the silicon substrate via lateral epitaxial overgrowth (LEO). ### Claim 14 (depends on 13) The method of claim 13 wherein growing a GaN wafer on the silicon substrate via LEO comprises: patterning a number of silicon pillars on a surface of the silicon substrate to provide a number of trenches on the surface of the silicon substrate; and growing the GaN wafer over the number of trenches. ### Claim 15 (depends on 12) The method of claim 12 wherein bonding a completed GaN layer to a completed silicon layer comprises: bonding the completed GaN layer to the completed silicon layer such that the completed GaN layer is disposed between the silicon substrate and the completed silicon layer. ### Claim 16 (depends on 15) The method of claim 15, further comprising: removing at least a portion of the silicon substrate from the completed GaN layer to expose at least a portion of a surface of the completed GaN layer. ### Claim 17 (depends on 9) The method of claim 9 wherein conductively coupling at least one integrated circuit on each of the number of GaN dies to at least one integrated circuit on each of the completed silicon dies comprises: patterning one or more conductive interconnect layers on the exposed portion of the surface of the completed GaN layer. ### Claim 18 (depends on 12) The method of claim 12 wherein bonding a completed GaN layer to a completed silicon layer comprises: bonding the completed GaN layer to a second silicon substrate such that the completed GaN layer is disposed between the silicon substrate and the second silicon substrate; removing at least a portion of the silicon substrate from the completed GaN layer to expose at least a portion of a surface of the completed GaN layer; and bonding the exposed portion of the surface of the completed GaN layer to the completed silicon layer such that the completed GaN layer is disposed between the second silicon substrate and the completed silicon layer. ### Claim 19 (depends on 18) The method of claim 18, further comprising: removing at least a portion of the second silicon substrate from the completed GaN layer to expose at least a portion of a second surface of the completed GaN layer. ### Claim 20 (depends on 19) The method of claim 19 wherein removing at least a portion of the second silicon substrate from the completed GaN layer to expose at least a portion of a second surface of the completed GaN layer comprises: removing the portion of the second silicon substrate from the completed GaN layer to expose at least the portion of the second surface of the completed GaN layer using at least one of: chemical etching, mechanical abrasion, or chemical-mechanical planarization (CMP). ### Claim 21 (depends on 20) The method of claim 20 wherein conductively coupling at least one integrated circuit on each of the number of GaN dies to at least one integrated circuit on each of the completed silicon dies comprises: patterning at least one interconnect layer on the exposed portion of the second surface of the completed GaN layer. ### Claim 22 (depends on 18) The method of claim 18 wherein bonding the completed GaN layer to a second silicon substrate such that the completed GaN layer is disposed between the silicon substrate and the second silicon substrate comprises: layer transferring the completed GaN layer to a second silicon substrate such that the completed GaN layer is disposed between the silicon substrate and the second silicon substrate. ### Claim 23 (depends on 18) The method of claim 18 wherein bonding the exposed portion of the surface of the completed GaN layer to the completed silicon layer such that the completed GaN layer is disposed between the second silicon substrate and the completed silicon layer comprises: layer transferring the exposed portion of the surface of the completed GaN layer to the completed silicon layer such that the completed GaN layer is disposed between the second silicon substrate and the completed silicon layer. ### Claim 24 A system for forming a compound semiconductor, the system comprising: a means for bonding a completed gallium nitride (GaN) layer including a number of completed GaN dies to a completed silicon layer including a number of completed silicon dies; and a means for conductively coupling at least one integrated circuit on each of the number of GaN dies to at least one integrated circuit on each of the completed silicon dies.