Multi-chip wafer level packages and methods of forming the same

A multi-chip wafer level package, comprising:

• a first redistribution layer structure;
• a chip module comprising:
• a first semiconductor chip over a first side of the first redistribution layer structure;
• a second semiconductor chip aside the first semiconductor chip and over the first side of the first redistribution layer structure;
• a second redistribution layer structure over the first semiconductor chip and the second semiconductor chip;
• a third semiconductor chip over the second redistribution layer structure and electrically connected to the first semiconductor chip;
• and
• a fourth semiconductor chip over the second redistribution layer structure and electrically connected to the second and third semiconductor chips;
• a plurality of bumps over a second side of the first redistribution layer structure opposite to the first side;
• and
• a fifth semiconductor chip and a sixth semiconductor chip disposed over the first side of the first redistribution layer and adjacent to the chip module,
• wherein at least one of the first and second semiconductor chips comprises an integrated passive device chip.

A multi-chip wafer level package, comprising:

• a first semiconductor chip over a first side of first redistribution layer structure;
• a second semiconductor chip aside the first semiconductor chip and over the first side of the first redistribution layer structure;
• a second redistribution layer structure over the first semiconductor chip and the second semiconductor chip;
• a third semiconductor chip over the second redistribution layer structure and electrically connected to the first semiconductor chip;
• a fourth semiconductor chip over the second redistribution layer structure and electrically connected to the second and third semiconductor chips;
• and
• a plurality of bumps over a second side of the first redistribution layer structure opposite to the first side,
• wherein the third semiconductor chip is electrically connected to the fourth semiconductor chip through an interposer between the first and second semiconductor chips.