# US 10,763,230 B2 · Integrated circuit backside metallization

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- Number: US 10,763,230 B2
- Document ID: US10763230B2
- Status: Granted
- Kind: B2
- Application number: 16/228,962
- Filed: 2018-12-21
- Published: 2020-06-25
- Granted: 2020-09-01
- Earliest claimed: 2018-12-21
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Hiroyuki Sada; Shoichi Iriguchi; Genki Yano; Luu Thanh Nguyen; Ashok Prabhu; Anindya Poddar; Yi Yan; Hau Nguyen
- Web page: https://patentgrep.com/patent/US10763230B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 72/742: {involving stretching of the auxiliary support post dicing}
- H10W 70/40: Leadframes
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/01923: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01961: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951)}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/354: {comprising polymers}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer comprising a plurality of dies, the pattern comprising a clearance area along a scribe line between the dies;
focusing a laser, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer, wherein the second surface is opposite the first surface, and the point is aligned with the clearance area; and
separating the dies along the scribe line.

### Claim 2 (depends on 1)

The method of claim 1, further comprising depositing an adhesion layer on the first side of the silicon wafer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising depositing a barrier layer on the adhesion layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the inkjet printing comprises printing the pattern of nanosilver conductive ink on the barrier layer, wherein the clearance area exposes the barrier layer.

### Claim 5 (depends on 3)

The method of claim 3, further comprising applying an atmospheric plasma to remove oxide from the barrier layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising curing the printed pattern of nanosilver conductive ink.

### Claim 7 (depends on 1)

The method of claim 1, further comprising detecting, through the silicon wafer, fiducial marks on the second surface of the silicon wafer to align an inkjet print nozzle to dispense the pattern of nanosilver conductive ink.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
bonding a given one of the dies to the die attach pad of a lead frame;
electrically coupling the given one of the dies to terminals of the lead frame via bond wires; and
enclosing the given one of the dies, the bond wires, and at least a portion of the lead frame in a case.