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US 10,763,222 B2Granted
Three-dimensional semiconductor devices having vertical structures of different lengths
AssigneeSamsung Electronics Co., Ltd.
InventorsJaeho Jeong, Sunyoung Kim, Jang-Gn Yun, Hoosung Cho, Sunghoi Hur
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Abstract
Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.
Claims20
A three-dimensional (3D) semiconductor device comprising:
- a substrate including a chip region and a scribe line region;
- a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate;
- a stack structure disposed on the scribe line region of the substrate, the stack structure including first layers and second layers that are vertically and alternately stacked;
- a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate, the plurality of vertical structures penetrating the stack structure;
- and
- a peripheral logic structure disposed between the cell array structure and the stack structure, the peripheral logic structure including peripheral logic circuits on the chip region of the substrate, and
- a dam pattern extending along an edge of the chip region and disposed between the stack structure and the cell array structure, the dam pattern surrounding the cell array structure,
- wherein the dam pattern is spaced apart from the stack structure and the cell array structure,
- wherein the stack structure has a staircase portion adjacent to the dam pattern and a vertically aligned sidewall opposite to the staircase portion,
- wherein the plurality of vertical structures including a first vertical structure penetrating the staircase portion and a second vertical structure penetrating the stack structure between the staircase portion and the vertically aligned sidewall, and
- wherein a vertical length of the first vertical structure is different from a vertical length of the second vertical structure.
8 more elements
A three-dimensional (3D) semiconductor device comprising:
- a substrate including a top surface comprising a chip region and a scribe line region;
- a cell array structure including a plurality of memory cells three-dimensionally arranged on the chip region of the substrate;
- a dam pattern extending along an edge of the chip region and surrounding the cell array structure, the dam pattern extending in a vertical direction that is substantially perpendicular to the top surface of the substrate;
- a stack structure disposed on the scribe line region of the substrate and being spaced apart from the dam pattern, the stack structure including first layers and second layers that are vertically and alternately stacked;
- a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate, the plurality of vertical structures penetrating the stack structure;
- and
- a peripheral logic structure disposed between the cell array structure and the stack structure, the peripheral logic structure including peripheral logic circuits on the chip region of the substrate,
- wherein the stack structure includes pad portions of which vertical distances from the top surface of the substrate, in the vertical direction, sequentially decrease as a horizontal distance from the chip region, in a direction that is parallel to the top surface of the substrate, decreases,
- wherein each of the first layers includes an insulating pattern and a conductive pattern, and
- wherein a side surface of the insulating pattern and a side surface of the conductive pattern contact each other.
7 more elements
A semiconductor device comprising:
- a substrate comprising a top surface comprising a cell array region, a dam region and a scribe line region, the dam region being disposed between the cell array region and the scribe line region;
- a stack structure on the cell array region of the top surface of the substrate, the stack structure comprising a plurality of insulating layers and a plurality of electrode layers that are disposed between adjacent ones of the insulating layers;
- a dummy stack structure on the scribe line region of the top surface of the substrate, the dummy stack structure comprising a plurality of dummy insulating layers that are aligned with ones of the plurality of insulating layers of the stack structure and a plurality of sacrificial layers that are disposed between adjacent ones of the dummy insulating layers and aligned with the electrode layers of the stack structure, the dummy stack structure comprising a sidewall surface extending in a vertical direction that is substantially perpendicular to the top surface of the substrate;
- a plurality of dummy vertical structures on the scribe line region of the top surface of the substrate, the plurality of dummy vertical structures extending in the vertical direction that is substantially perpendicular to the top surface of the substrate and spaced apart from each other in a first direction that is parallel to the top surface of the substrate, and
- a dam pattern on the dam region of the top surface of the substrate, the dam pattern extending in the vertical direction that is substantially perpendicular to the top surface of the substrate,
- wherein the dam pattern is spaced apart from the stack structure and the dummy stack structure, and
- wherein the plurality of sacrificial layers are formed of a different material from the plurality of electrode layers.
4 more elements
Dependencies are inferred from the claim text.