HV converter with reduced EMI

A power semiconductor package comprising:

• a lead frame comprising
• a source section;
• and
• a drain section;
• a first semiconductor chip including a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame, the first semiconductor chip comprising
• a source electrode disposed on a first surface of the first semiconductor chip, the source electrode being electrically connected to the source section of the lead frame, the first surface facing the lead frame;
• and
• a drain electrode of the first semiconductor chip being electrically connected to the drain section of the lead frame;
• a molding encapsulation;
• and
• a second semiconductor chip comprising a semiconductor transistor;
• wherein the first semiconductor chip and a majority portion of the lead frame are embedded in the molding encapsulation;
• wherein a bottom surface area of the source section exposed from the molding encapsulation is larger than a bottom surface area of the drain section exposed from the molding encapsulation so as to reduce an electromagnetic interference (EMI) noise for high voltage applications;
• and
• wherein a chip size of the second semiconductor chip is less than twenty percent of a chip size of the first semiconductor chip.

A high voltage converter implemented on a printed circuit board (PCB), the high voltage converter comprising:

• a transformer comprising a primary winding and a secondary winding;
• a power semiconductor package comprising a first switch comprising
• a source electrode connected to a source lead;
• and
• a drain electrode connected to a drain lead;
• wherein the drain lead is attached to a drain copper pad on the PCB such that the drain electrode of the first switch is electrically connected to a first terminal of the primary winding of the transformer;
• wherein the source lead is attached to a source copper pad on the PCB;
• and
• wherein an area the source lead contacting the source copper pad on the PCB is larger than an area the drain lead contacting the drain copper pad on the PCB.

A power semiconductor package comprising:

• a lead frame comprising
• a source section;
• and
• a drain section;
• a first semiconductor chip including a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame, the first semiconductor chip comprising
• a source electrode disposed on a first surface of the first semiconductor chip, the source electrode being electrically connected to the source section of the lead frame, the first surface facing the lead frame;
• and
• a drain electrode of the first semiconductor chip being electrically connected to the drain section of the lead frame;
• and
• a molding encapsulation;
• wherein the first semiconductor chip and a majority portion of the lead frame are embedded in the molding encapsulation;
• wherein a bottom surface area of the source section exposed from the molding encapsulation is larger than a bottom surface area of the drain section exposed from the molding encapsulation so as to reduce an electromagnetic interference (EMI) noise for high voltage applications;
• and
• wherein the bottom surface area of the source section exposed from the molding encapsulation is more than ten times the bottom surface area of the drain section exposed from the molding encapsulation.