Integrated circuit having a hidden shared contact

An integrated circuit comprising:

• a semiconductor substrate including at least one substrate zone delineated by an insulating zone;
• a polysilicon region having at least one part situated on said insulating zone, said at least one part of the polysilicon region having a side edge and, at a base of the at least one part, a strip extending perpendicularly away from the side edge above the insulating zone in a direction of said at least one substrate zone;
• an interconnection part;
• an isolating region situated between the substrate and said interconnection part and covering said at least one substrate zone and said polysilicon region;
• an electrically conductive pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and a second end in electrical contact with said interconnection part;
• and
• at least one MOS transistor produced on and in an active zone delineated by the insulating region, said active zone having a source region and a drain region, and said substrate zone being one of the source and drain regions.

An integrated circuit, comprising:

• a semiconductor substrate including at least one substrate zone delineated by an insulating zone;
• a polysilicon region having at least one part situated on said insulating zone, said at least one part of the polysilicon region having a side edge and, at a base of the at least one part, a strip extending perpendicularly away from the side edge above the insulating zone in a direction of said at least one substrate zone;
• an interconnection part;
• an isolating region situated between the substrate and said interconnection part and covering said at least one substrate zone and said polysilicon region;
• and
• an electrically conductive pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and a second end in electrical contact with said interconnection part;
• wherein said polysilicon region is a part of a gate region of another transistor.

A method for producing, within an integrated circuit, at least one shared electrically conductive contact pad between a substrate zone situated in a semiconductor substrate of the integrated circuit and delineated by an insulating zone, and a polysilicon region having at least one part situated on said insulating zone, the method comprising:

• forming said polysilicon region by forming, at a base of said at least one part of the polysilicon region, a strip extending perpendicularly away from a side edge of said at least one part and above the insulating zone in the direction of said substrate zone;
• forming an isolating region situated above the semiconductor substrate and covering said substrate zone and said polysilicon region;
• forming said at least one shared electrically conductive contact pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and having a second end;
• and
• forming an interconnection region of the integrated circuit in electrical contact with said second end of said at least one shared electrically conductive contact pad;
• and
• siliciding said portion of the strip.

A method for producing, within an integrated circuit, at least one shared electrically conductive contact pad between a substrate zone situated in a semiconductor substrate of the integrated circuit and delineated by an insulating zone, and a polysilicon region having at least one part situated on said insulating zone, the method comprising:

• forming said polysilicon region by forming, at a base of said at least one part of the polysilicon region, a strip extending perpendicularly away from a side edge of said at least one part and above the insulating zone in the direction of said substrate zone;
• forming an isolating region situated above the semiconductor substrate and covering said substrate zone and said polysilicon region;
• forming said at least one shared electrically conductive contact pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and having a second end;
• and
• forming an interconnection region of the integrated circuit in electrical contact with said second end of said at least one shared electrically conductive contact pad;
• and
• producing, prior to forming said at least shared one electrically conductive contact pad, at least one MOS transistor on and in an active zone situated in the semiconductor substrate and delineated by said insulating zone, said active zone having a source region and a drain region, and said substrate zone being one of the source and drain regions.

An integrated circuit, comprising:

• a semiconductor substrate including a first active region delimited by an insulating region;
• a first doped region within the first active region;
• a second doped region within the first active region;
• a strip of polysilicon extending over said insulating region and including a first portion having a first thickness and a second portion having a second thickness that is less than the first thickness;
• a pre-metal dielectric layer covering the semiconductor substrate and the strip of polysilicon;
• a first contact extending through the pre-metal dielectric layer and having an end that makes contact with both the first doped region and the second portion of the strip of polysilicon;
• and
• a second contact extending through the pre-metal dielectric layer and having an end that makes contact with the second doped region;
• wherein a cross section of the first contact and a cross section of the second contact have identical or substantially identical sizes, to within a tolerance.