# US 10,763,211 B2 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,763,211 B2 - Document ID: US10763211B2 - Status: Granted - Kind: B2 - Application number: 16/048,921 - Filed: 2018-07-30 - Published: 2018-12-06 - Granted: 2020-09-01 - Earliest claimed: 2016-07-26 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Ming-Han Lee; Shau-Lin Shue - Web page: https://patentgrep.com/patent/US10763211B2 ## CPC - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10W 20/033: {in openings in dielectrics} - H10W 20/034: {bottomless barrier, adhesion or liner layers} - H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal} - H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)} - H10W 20/082: {the openings being tapered via holes} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/42: Vias, e.g. via plugs - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/4437: {the principal metal being a transition metal} - H10W 20/48: Insulating materials thereof - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer. ## Claims ### Claim 1 A semiconductor device, comprising: a first interlayer dielectric (ILD) layer disposed over a substrate; a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate; a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern, wherein: in a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is at least partially covered by a first two-dimensional material layer, in the cross section, sides and bottom of the first metal wiring pattern are covered by a second two-dimensional material layer, the first and second two-dimensional material layers are single layers of two-dimensional material, the first two-dimensional material layer and the second two-dimensional material layer are different materials, the first two-dimensional material layer is disposed only over the first metal wiring pattern, and the second metal wiring pattern passes through the first two-dimensional material layer and is in direct contact with a surface of the first metal wiring pattern. ### Claim 2 (depends on 1) The semiconductor device of claim 1 wherein the first and second metal wiring patterns include Cu, and the second metal wiring pattern passing through the first two-dimensional material layer is in direct contact with a Cu surface of the first metal wiring pattern. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first two-dimensional material layer and the second two-dimensional material layer include graphene, a transition metal dichalcogenide (TMD), or BN. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the TMD includes one of MoS2, WS2 and NbSe2. ### Claim 5 A semiconductor device, comprising: a first interlayer dielectric (ILD) layer disposed over a substrate; a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate, wherein the first metal wiring pattern includes a first lower portion and a first upper portion; a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern, wherein the second metal wiring pattern includes a second lower portion and a second upper portion, in a cross section along a second direction, which crosses the first direction and is in parallel with the substrate, a top of the second metal wiring pattern is fully covered by a first two-dimensional material layer, the first two-dimensional material layer is a single layer of two-dimensional material, and the first two-dimensional material layer is in direct contact with a surface of the second metal wiring pattern, wherein in the cross section, sides and bottom of the upper portion of the second metal wiring pattern are covered by a second two-dimensional material layer, in the cross section, a part of a top of the first metal wiring pattern is covered by a third two-dimensional material layer, and the second metal wiring pattern passes through the third two-dimensional material layer and is in direct contact with a surface of the first metal wiring pattern, in the cross section, sides and bottom of the upper portion of the first metal wiring pattern are covered by a fourth two-dimensional material layer, and wherein the first two-dimensional material layer and the second two-dimensional material layer are different materials. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the first two-dimensional material layer covering the top of the second metal wiring pattern only covers the second metal wiring pattern. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the third two-dimensional material layer covering the top of the first metal wiring pattern only covers the first metal wiring pattern. ### Claim 8 (depends on 5) The semiconductor device of claim 5, wherein: the first and second metal wiring patterns include Cu, and the first two-dimensional material layer is in direct contact with a Cu surface of the second metal wiring pattern. ### Claim 9 (depends on 5) The semiconductor device of claim 5, wherein the lower portion of the second metal wiring pattern is in direct contact with a Cu surface of the first metal wiring pattern. ### Claim 10 (depends on 5) The semiconductor device of claim 5, wherein the third two-dimensional material layer and the fourth two-dimensional material layer include a same material. ### Claim 11 (depends on 5) The semiconductor device of claim 5, wherein the third two-dimensional material layer and the fourth two-dimensional material layer are different materials. ### Claim 12 A method of manufacturing a semiconductor device, comprising: forming a first interlayer dielectric layer over a substrate; forming a first recess in the first interlayer dielectric layer; forming a first conductive material layer in a lower portion of the first recess; forming a single layer of a first two-dimensional material layer over the first conductive material layer and sidewalls of the first recess above the first conductive material layer; forming a first metal layer in the first recess over the first two-dimensional material layer; forming a single layer of a second two-dimensional material layer over the first metal layer; forming a second interlayer dielectric layer over the second two-dimensional material layer and the first interlayer dielectric layer; forming a second recess in the second interlayer dielectric layer exposing the second two-dimensional material layer; forming a second conductive material layer in a lower portion of the second recess; forming a single layer of a third two-dimensional material layer over the second conductive material layer and sidewalls of the second recess above the second conductive material layer; forming a second metal layer in the second recess over the third two-dimensional material layer; and forming a single layer of a fourth two-dimensional material layer over the second metal layer. ### Claim 13 (depends on 12) The method according to claim 12, further comprising removing a metal oxide layer on an upper surface of the first metal wiring pattern before forming the second two-dimensional material layer, wherein the metal oxide layer is a metal oxide of the first metal wiring pattern. ### Claim 14 (depends on 12) The method according to claim 12, further comprising partially removing the second two-dimensional material layer to expose an upper surface of the first metal wiring pattern before forming the second conductive material layer. ### Claim 15 (depends on 12) The method according to claim 12, wherein the fourth two-dimensional material layer covering the top of the second metal wiring pattern only covers the second metal wiring pattern. ### Claim 16 (depends on 12) The method according to claim 12, wherein the first two-dimensional material layer and the second two-dimensional layer are different materials. ### Claim 17 (depends on 1) The semiconductor device of claim 1, wherein the first ILD layer is made of a low-k material having a dielectric constant k lower than 3.5. ### Claim 18 (depends on 1) The semiconductor device of claim 1, wherein the first ILD layer is made of a low-k material having a dielectric constant k lower than 2.5. ### Claim 19 (depends on 1) The semiconductor device of claim 1, wherein the first ILD layer is made of one or more layers of a carbon-containing material, organosilicate glass, a porogen-containing material, or combinations thereof. ### Claim 20 (depends on 1) The semiconductor device of claim 1, wherein the first ILD layer comprises one or more selected from the group consisting of a silicon oxide, silicon nitride, SiON, SiOC, SiOCN, and SiCOH.