US 10,763,209 B2 · MOS antifuse with void-accelerated breakdown

Abstract

A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

Claims21

Dependent claims

A metal-oxide-semiconductor (MOS) antifuse structure comprising:

a semiconductor channel region;
a source region and a drain region on opposite sides of the channel region, wherein at least one of the source and drain regions is to be a first terminal of the antifuse structure;
a source contact interfacing with the source region and a drain contact interfacing with the drain region;
a gate dielectric over the channel region;
and
a gate electrode separated from the channel region by the gate dielectric and separated from the drain and source contacts by an intervening dielectric material, the gate electrode to be a second terminal of the antifuse structure, and the gate electrode having a seam extending from a top surface of the gate electrode and exposing the gate dielectric.

3 more elements

Dependencies are inferred from the claim text.

MOS antifuse with void-accelerated breakdown

Life of this patent

MOS antifuse with void-accelerated breakdown

Life of this patent

Abstract

Claims21