Method of fabricating integrated fan-out packages

A method, comprising:

• forming a redistribution circuit structure on an integrated circuit component laterally encapsulated by an insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the integrated circuit component, and forming the redistribution circuit structure comprising:
• forming a first conductive via on the integrated circuit component;
• forming a first dielectric layer on the integrated circuit component and the insulating encapsulation to cover the first conductive via;
• performing a first polishing process to polish the first dielectric layer until the first conductive via is exposed, wherein a sidewall of the first conductive via or a sidewall of the first dielectric layer is exposed after performing the first polishing process;
• forming a first seed layer and a first redistribution wiring on the first conductive via and a portion of the first dielectric layer, wherein the sidewall of the first conductive via or the sidewall of the first dielectric layer is covered by the first seed layer;
• forming a second conductive via on the first redistribution wiring;
• forming a second dielectric layer on the first dielectric layer to cover the second conductive via and the first redistribution wiring;
• and
• performing a second polishing process to polish the second dielectric layer until the second conductive via is exposed.

A method, comprising:

• forming a redistribution circuit structure on an integrated circuit component laterally encapsulated by an insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the integrated circuit component, and forming the redistribution circuit structure comprising:
• forming a first conductive via on the integrated circuit component;
• forming a first dielectric layer on the integrated circuit component and the insulating encapsulation to cover the first conductive via;
• performing a first polishing process to polish the first dielectric layer until a first level height offset is present between exposed top surfaces of the first conductive via and the first dielectric layer;
• and
• forming a first seed layer and a first redistribution wiring over the first conductive via, the first seed layer being in contact with a portion of the first dielectric layer.