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US 10,763,160 B1Granted
Semiconductor device with selective insulator for improved capacitance
AssigneeInternational Business Machines Corporation
InventorsChristopher J. Penny, Benjamin D. Briggs, Michael Rizzolo, Lawrence A. Clevenger, Huai Huang, Hosadurga Shobha
Life of this patent
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Abstract
Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.
Claims17
A method for forming a semiconductor device, the method comprising:
- forming an alternating arrangement of vertical metallic lines and vertical dielectric spacers on a substrate;
- recessing the vertical dielectric spacers below a top surface of the vertical metallic lines;
- selectively depositing an interlevel dielectric layer on the recessed vertical dielectric spacers and above the top surface of the vertical metallic lines;
- depositing a dielectric fill on the interlevel dielectric layer and over the top surface of the vertical metallic lines;
- patterning a photoresist on the dielectric fill to form a plurality of openings in the photoresist, wherein a first opening of the photoresist is in vertical alignment with a first vertical dielectric spacer and a second opening of the photoresist is in vertical alignment with a second vertical dielectric spacer, and further wherein at least a third vertical dielectric spacer and a fourth vertical dielectric spacer are disposed between the first vertical dielectric spacer and the second vertical dielectric spacer;
- selectively etching the dielectric fill and the interlevel dielectric layer in the first opening and the second opening to expose a top surface of the respective first vertical dielectric spacer and the second vertical dielectric spacer;
- removing the photoresist and the dielectric fill;
- and
- removing the vertical dielectric spacers to expose the top surfaces of the substrate in the first opening and the second opening and the vertical metallic lines, and wherein the interlevel dielectric layer seals an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer in place of third vertical dielectric spacer and the fourth vertical dielectric spacer.
6 more elements
A method for forming a semiconductor device, the method comprising:
- forming an alternating arrangement of vertical metallic lines and vertical dielectric spacers on a substrate;
- recessing the vertical metallic lines below a top surface of the vertical dielectric spacers;
- selectively depositing an interlevel dielectric layer on the vertical dielectric spacers and on sidewalls in the recessed vertical metallic lines leaving an opening therebetween and exposing a top surface of the recessed vertical metallic lines;
- depositing a dielectric fill on the interlevel dielectric layer and in the openings;
- patterning a photoresist on the dielectric fill to form a plurality of openings in the photoresist, wherein a first opening of the photoresist is in vertical alignment with a first vertical dielectric spacer and a second opening of the photoresist is in vertical alignment with a second vertical dielectric spacer, and further wherein at least a third vertical dielectric spacer and a fourth vertical dielectric spacer are disposed between the first vertical dielectric spacer and the second vertical dielectric spacer;
- selectively etching the dielectric fill and the interlevel dielectric layer in the first opening and the second opening to expose a top surface of the first vertical dielectric spacer and the second vertical dielectric spacer;
- removing the photoresist;
- and
- removing the vertical dielectric spacers to expose the top surfaces of the substrate in the first opening and the second opening and the vertical metallic lines, and wherein the first interlevel dielectric layer seals an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer in place of third vertical dielectric spacer and the fourth vertical dielectric spacer.
6 more elements
Dependencies are inferred from the claim text.