# US 10,763,158 B2 · Method for forming lead wires in hybrid-bonded semiconductor devices

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- Number: US 10,763,158 B2
- Document ID: US10763158B2
- Status: Granted
- Kind: B2
- Application number: 16/126,935
- Filed: 2018-09-10
- Published: 2019-03-21
- Granted: 2020-09-01
- Earliest claimed: 2018-08-03
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Meng Yan; Jifeng Zhu; Si Ping Hu
- Web page: https://patentgrep.com/patent/US10763158B2

## CPC

- H10W 20/081: {by forming openings in the dielectric parts}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of hybrid-bonded semiconductor structures and methods for forming a hybrid-bonded semiconductor structure are disclosed. The method can include providing a substrate and forming a base dielectric layer on the substrate. The method also includes forming first and second conductive structures in the base dielectric layer and disposing an alternating dielectric layer stack. Disposing alternating dielectric layer stack includes disposing a first dielectric layer on the base dielectric layer and the first and second conductive structures and sequentially disposing second, third, and fourth dielectric layers. The method further includes planarizing the disposed alternating dielectric layer stack and etching the alternating dielectric layer stack to form first and second openings using preset etching rates for each of the first, second, third, and fourth dielectric layers. The etching continues until at least portions of the first and second conductive structures are exposed. The method also includes forming conductive material in the first and second openings to form lead wires.

## Claims

### Claim 1

A method for forming lead wires in a semiconductor structure, the method comprising:
forming a base dielectric layer on a substrate;
forming first and second conductive structures in the base dielectric layer;
disposing an alternating dielectric layer stack, comprises:
disposing a first dielectric layer on the base dielectric layer and the first and second conductive structures; and
sequentially disposing second, third, and fourth dielectric layers,
wherein at least two of the first, second, third, and fourth dielectric layers have non-uniform thickness and non-uniform surface flatness;
planarizing the disposed alternating dielectric layer stack;
forming first and second openings in the alternating dielectric layer stack using preset etching rates for each of the first, second, third, and fourth dielectric layers, wherein the forming the first and second openings continues until at least portions of the first and second conductive structures are exposed; and
disposing conductive material in the first and second openings to form lead wires.

### Claim 2 (depends on 1)

The method of claim 1, wherein the disposing the first and third dielectric layers comprises disposing silicon nitride layers using chemical vapor deposition (CVD) processes.

### Claim 3 (depends on 1)

The method of claim 1, wherein the disposing the second and fourth dielectric layers comprises disposing silicon oxide layers using CVD processes.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the base dielectric layer comprises disposing a dielectric material using CVD processes.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming the first and second conductive structures comprises:
etching trenches in the base dielectric layer based on a circuit layout design;
disposing conductive material into the trenches and on the base dielectric layer; and
removing the conductive material disposed on the base dielectric layer such that top surfaces of the conductive material in the trenches are coplanar with a top surface of the base dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the disposing the alternating dielectric layer stack further comprises:
disposing the second dielectric layer on a top surface of the first dielectric layer;
disposing the third dielectric layer on a top surface of the second dielectric layer; and
disposing the fourth dielectric layer on a top surface of the third dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the disposing the first and third dielectric layers comprises disposing silicon nitride.

### Claim 8 (depends on 1)

The method of claim 1, wherein the disposing the second and fourth dielectric layers comprises disposing silicon oxide.

### Claim 9 (depends on 1)

The method of claim 1, wherein the preset etching rates vary during the etching.

### Claim 10 (depends on 1)

The method of claim 1, wherein the forming the first and second openings further comprises:
a first etching step comprising etching the fourth dielectric layer in the first and second openings, wherein the preset etching rates are the same in the first and second openings during the first etching step;
a second etching step comprising etching the third and fourth dielectric layers in the first and second openings respectively, wherein the preset etching rates are different in the first and second openings during the second etching step;
a third etching step comprising etching the second and third dielectric layers in the first and second openings, wherein the preset etching rates are the same in the first and second openings during the third etching step;
a fourth etching step comprising etching the first dielectric layer in the first opening and the second dielectric layer in the second opening, wherein the preset etching rates are different in the first and second openings during the fourth etching step; and
a fifth etching step comprising etching the first dielectric layer in the first and second openings, wherein the preset etching rates are the same in the first and second openings during the fifth etching step.

### Claim 11

A method for forming a semiconductor structure, the method comprising:
forming a base dielectric layer on a substrate;
forming first and second conductive structures in the base dielectric layer;
disposing a first dielectric layer on the base dielectric layer and the first and second conductive structures;
sequentially disposing second, third, and fourth dielectric layers, wherein at least two of the first, second, third, and fourth dielectric layers have non-uniform thickness and non-uniform surface flatness;
forming first and second openings by etching the fourth dielectric layer using same preset etching rates in the first and second openings;
etching the third and fourth dielectric layers in the first and second openings respectively using different preset etching rates in the first and second openings;
etching the second and third dielectric layers in the first and second openings using same preset etching rates in the first and second openings;
etching the first dielectric layer in the first opening and the second dielectric layer in the second opening using different etching rates in the first and second openings;
etching the first dielectric layer in the first and second openings using same preset etching rates in the first and second openings to expose portions of the first and second conductive structures; and
forming conductive material in the first and second openings and on the exposed portions of the first and second conductive structures to form lead wires.

### Claim 12 (depends on 11)

The method of claim 11, wherein disposing the first and third dielectric layers comprise disposing silicon nitride layers using chemical vapor deposition (CVD) processes.

### Claim 13 (depends on 11)

The method of claim 11, wherein disposing the second and fourth dielectric layers comprise disposing silicon oxide layers using CVD processes.

### Claim 14 (depends on 11)

The method of claim 11, wherein forming the base dielectric layer comprises disposing a dielectric material using CVD processes.

### Claim 15 (depends on 11)

The method of claim 11, wherein forming the first and second conductive structures comprises:
etching trenches in the base dielectric layer based on a circuit layout design;
disposing conductive material into the trenches and on the base dielectric layer; and
removing the conductive material disposed on the base dielectric layer such that top surfaces of the conductive material in the trenches are coplanar with a top surface of the base dielectric layer.