Lithographic technique for feature cut by line-end shrink
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu
Estimating the term…
A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.
A method comprising:
A method of patterning a workpiece, the method comprising:
A method of patterning a material layer, the method comprising:
Dependencies are inferred from the claim text.