Memory storage device and memory testing method thereof
AssigneeWinbond Electronics Corp.
InventorsKuen-Huei Chang, Che-Min Lin
Life of this patent
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Abstract
A memory storage device and a memory testing method for testing a memory array of the memory storage device are provided. The memory testing method includes the following steps: writing first data into a plurality of first segments of the memory array, and writing second data to a second segment of the memory array; obtaining third data by reading the plurality of first segments, and obtaining fourth data by reading the second segment; converting the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to a decoding circuit of the memory storage device.
Claims12
A memory testing method, for testing a memory array of a memory storage device, the memory testing method comprising:
- writing first data into a plurality of first segments of the memory array, and writing second data into a second segment of the memory array;
- obtaining third data by reading the plurality of first segments, and obtaining fourth data by reading the second segment;
- and
- converting the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to a decoding circuit of the memory storage device.
A memory storage device, comprising:
- a memory array, comprising a plurality of first segments and a second segment;
- and
- a memory controlling circuit, comprising:
- a data writing circuit coupled to the memory array and configured to write first data into the plurality of first segments and write second data into the second segment;
- a data reading circuit coupled to the memory array and configured to obtain third data by reading the plurality of first segments and obtain fourth data by reading the second segment;
- a decoding circuit coupled to the data reading circuit;
- and
- a data converting circuit coupled between the data reading circuit and the decoding circuit and configured to convert the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to the decoding circuit.
Dependencies are inferred from the claim text.