# US 10,762,976 B2 · Scan driving circuit, driving method, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,762,976 B2 - Document ID: US10762976B2 - Status: Granted - Kind: B2 - Application number: 16/197,521 - Filed: 2018-11-21 - Published: 2019-10-31 - Granted: 2020-09-01 - Earliest claimed: 2018-04-28 - Assignees: Shanghai Tianma Am-Oled Co., Ltd. - Applicants: Shanghai Tianma AM-OLED Co., Ltd. - Inventors: Renyuan Zhu; Yue Li; Dongxu Xiang; Yana Gao; Xingyao Zhou; Gaojun Huang; Yilin Xu; Zhonglan Cai; Juan Zhu - Web page: https://patentgrep.com/patent/US10762976B2 ## CPC - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/04: Display protection - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C: STATIC STORES (semiconductor memory devices H10B) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The present disclosure provides a shift register. The shift register includes: a first node control module for controlling level at the first node; a second node control module for controlling level at a second node; and an output control module for controlling the output terminal to output high or low level. The first node control module includes an input unit configured to write the input signal into the third node and a protection unit configured to control a level at a fourth node based on a level at the third node and control writing of the level at the fourth node into the first node based on the second clock signal. The technical solution of the present disclosure can prevent the transistor for providing the third node with inputting signal from being broken down. ## Claims ### Claim 1 A scan driving circuit, comprising a plurality of cascaded shift registers, wherein a shift register at each stage of the plurality of cascaded shift registers comprises: a first node control module; a second node control module; and an output control module, wherein the first node control module is electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal, a high level signal terminal, a first node, a second node and a third node, and configured to control a level at the first node based on an input signal, a first clock signal, a second clock signal, a high level signal and a level at the second node, wherein the first node control module comprises an input unit configured to write the input signal into the third node and a protection unit configured to control a level at a fourth node based on a level at the third node and control writing of the level at the fourth node into the first node based on the second clock signal, the second node control module is electrically connected to the first clock signal terminal, a low level signal terminal and the second node, and configured to control the level at the second node based on the first clock signal and the low level signal, and the output control module is electrically connected to the first node, the second node, the high level signal terminal, the second clock signal terminal and a scan signal output terminal, and configured to control the scan signal output terminal to output a high level or a low level based on the level at the first node and the level at the second node. ### Claim 2 (depends on 1) The scan driving circuit according to claim 1, wherein the input unit has a control terminal electrically connected to the first clock signal terminal, an input terminal electrically connected to the input signal terminal and an output terminal electrically connected to the third node, and the protection unit has a control terminal electrically connected to the third node, another control terminal electrically connected to the second clock signal terminal, an output terminal electrically connected to the first node, an input terminal electrically connected to the fourth node, and another input terminal electrically connected to the second clock signal terminal, wherein the level at the third node controls writing of the second clock signal into the fourth node, and the second clock signal controls writing of the level at the fourth node into the first node. ### Claim 3 (depends on 2) The scan driving circuit according to claim 2, wherein the input unit comprises a first transistor, and the protection unit comprises a second transistor and a third transistor, wherein the first transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal and a second terminal electrically connected to the third node, the second transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second clock signal terminal and a second terminal electrically connected to the fourth node, and the third transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the first node and a second terminal electrically connected to the fourth node. ### Claim 4 (depends on 3) The scan driving circuit according to claim 3, wherein the first node control module further comprises a fourth transistor having a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal and a second terminal electrically connected to the fourth node. ### Claim 5 (depends on 3) The scan driving circuit according to claim 3, wherein the first node control module further comprises a first capacitor having a first electrode electrically connected to the high level signal terminal and a second electrode electrically connected to the third node. ### Claim 6 (depends on 3) The scan driving circuit according to claim 3, wherein the first node control module further comprises a second capacitor having a first electrode electrically connected to the scan signal output terminal and a second electrode electrically connected to the first node. ### Claim 7 (depends on 3) The scan driving circuit according to claim 3, wherein the first transistor has a channel with a width to length ratio of 4:8. ### Claim 8 (depends on 1) The scan driving circuit according to claim 1, wherein the second node control module comprises a fifth transistor, a sixth transistor and a third capacitor, wherein the fifth transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the first clock signal terminal and a second terminal electrically connected to the second node, the sixth transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the low level signal terminal and a second terminal electrically connected to the second node, and the third capacitor has a first electrode electrically connected to the high level signal terminal and a second electrode electrically connected to the second node. ### Claim 9 (depends on 1) The scan driving circuit according to claim 1, wherein the output control module comprises a seventh transistor and an eighth transistor, wherein the seventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal and a second terminal electrically connected to the scan signal output terminal, and the eighth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the second clock signal terminal and a second terminal electrically connected to the scan signal output terminal. ### Claim 10 (depends on 1) The scan driving circuit according to claim 1, further comprising a first signal line, and a second signal line, wherein each first clock signal terminal of the shift register at each odd-numbered stage of the plurality of cascaded shift registers and the second clock signal terminal of the shift register at each even-numbered stage of the plurality of cascaded shift registers are both electrically connected to the first signal line, and the second clock signal terminal of the shift register at each odd-numbered stage of the plurality of cascaded shift registers and the first clock signal terminal of the shift register at each even-numbered stage of the plurality of cascaded shift registers are both electrically connected to the second signal line. ### Claim 11 (depends on 10) The scan driving circuit according to claim 10, wherein the input signal terminal of a shift register at an nth stage of the plurality of cascaded shift registers is electrically connected to the scan signal output terminal of a shift register at an (n−1)th stage of the plurality of cascaded shift registers, wherein n is 2, 3, 4, . . . , N, and N is a number of the plurality of cascaded shift registers in the scan driving circuit. ### Claim 12 A display device, comprising a scan driving circuit, the scan driving circuit comprising a plurality of cascaded shift registers, wherein a shift register at each stage of the plurality of cascaded shift registers, comprising comprises: a first node control module; a second node control module; and an output control module, wherein the first node control module is electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal, a high level signal terminal, a first node, a second node and a third node, and configured to control a level at the first node based on respective levels of an input signal, a first clock signal, a second clock signal, a high level signal and the second node, wherein the first node control module comprises an input unit configured to write the input signal into the third node and a protection unit configured to control a level at a fourth node based on a level at the third node and control writing of the level at the fourth node into the first node based on the second clock signal, the second node control module is electrically connected to the first clock signal terminal, a low level signal terminal and the second node, and configured to control a the level at the second node based on the first clock signal and the low level signal, and the output control module is electrically connected to the first node, the second node, the high level signal terminal, the second clock signal terminal and a scan signal output terminal, and configured to control the scan signal output terminal to output a high level or a low level based on the level at the first node and the level at the second node. ### Claim 13 A method for driving a shift register of a scan driving circuit, the scan driving circuit comprising a plurality of cascaded shift registers, wherein a shift register at each stage of the plurality of cascaded shift registers, comprising comprises: a first node control module; a second node control module; and an output control module, wherein the first node control module is electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal, a high level signal terminal, a first node, a second node and a third node, and configured to control a level at the first node based on respective levels of an input signal, a first clock signal, a second clock signal, a high level signal and the second node, wherein the first node control module comprises an input unit configured to write the input signal into the third node and a protection unit configured to control a level at a fourth node based on a level at the third node and control writing of the level at the fourth node into the first node based on the second clock signal, the second node control module is electrically connected to the first clock signal terminal, a low level signal terminal and the second node, and configured to control a the level at the second node based on the first clock signal and the low level signal, and the output control module is electrically connected to the first node, the second node, the high level signal terminal, the second clock signal terminal and a scan signal output terminal, and configured to control the scan signal output terminal to output a high level or a low level based on the level at the first node and the level at the second node, wherein the method comprises: maintaining, by the first node control module, the first node at a high level of a previous phase; providing, by the second node control module, a low level at the second node; and controlling, by the output control module, the scan signal output terminal to output a high level, in a first phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a low level and the second clock signal provided by the second clock signal terminal is at a high level; providing, by the first node control module, a low level at the first node; providing, by the second node control module, a high level at the second node; and controlling, by the output control module, the scan signal output terminal to output a low level, in a second phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a high level, and the second clock signal provided by the second clock signal terminal is at a low level; maintaining, by the first node control module, the first node at the low level of the second phase; providing, by the second node control module, a low level at the second node; and controlling, by the output control module, the scan signal output terminal to output a high level, in a third phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a low level, and the second clock signal provided by the second clock signal terminal is at a high level; and providing, by the first node control module, a high level at the first node; maintaining, by the second node control module, the second node at the low level of the third phase; and controlling, by the output control module, the scan signal output terminal to output a high level, in a fourth phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a high level, and the second clock signal provided by the second clock signal terminal is at a low level. ### Claim 14 (depends on 13) The method according to claim 13, wherein the low level of the first clock signal and the low level of the second clock signal are both equal to the low level of the low level signal, and the high level of the first clock signal and the high level of the second clock signal are both equal to the high level of the high level signal. ### Claim 15 (depends on 13) The method according to claim 13, wherein the input unit has a control terminal electrically connected to the first clock signal terminal, an input terminal electrically connected to the input signal terminal and an output terminal electrically connected to the third node, and the protection unit has a control terminal electrically connected to the third node, another control terminal electrically connected to the second clock signal terminal, an output terminal electrically connected to the first node, an input terminal electrically connected to the fourth node, and another input terminal electrically connected to the second clock signal terminal, wherein the level at the third node controls writing of the second clock signal into the fourth node, and the second clock signal controls writing of the level at the fourth node into the first node. ### Claim 16 (depends on 15) The method according to claim 15, wherein the input unit comprises a first transistor, and the protection unit comprises a second transistor and a third transistor, wherein the first transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal and a second terminal electrically connected to the third node, the second transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second clock signal terminal and a second terminal electrically connected to the fourth node, and the third transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the first node and a second terminal electrically connected to the fourth node. ### Claim 17 (depends on 16) The method according to claim 16, wherein the first node control module further comprises a fourth transistor having a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal and a second terminal electrically connected to the fourth node. ### Claim 18 (depends on 16) The method according to claim 16, wherein the first node control module further comprises a first capacitor having a first electrode electrically connected to the high level signal terminal and a second electrode electrically connected to the third node. ### Claim 19 (depends on 13) The method according to claim 13, wherein the second node control module comprises a fifth transistor, a sixth transistor and a third capacitor, wherein the fifth transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the first clock signal terminal and a second terminal electrically connected to the second node, the sixth transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the low level signal terminal and a second terminal electrically connected to the second node, and the third capacitor has a first electrode electrically connected to the high level signal terminal and a second electrode electrically connected to the second node. ### Claim 20 (depends on 13) The method according to claim 13, wherein the output control module comprises a seventh transistor and an eighth transistor, wherein the seventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal and a second terminal electrically connected to the scan signal output terminal, and the eighth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the second clock signal terminal and a second terminal electrically connected to the scan signal output terminal.