Shift register circuit, driving method thereof, and display device

A driving method of a shift register circuit comprising N cascaded shift register units, wherein the shift register units of odd-numbered stages receive a first clock signal, and the shift register units of even-numbered stages receive a second clock signal, N is an integer and N≥4, wherein the shift register circuit further comprises:

• a first switching unit configured to be turned on in response to a gate drive signal and to transmit the gate drive signal to an input terminal of the shift register unit of the second stage;
• a second switching unit configured to be turned on in response to an output signal of the shift register unit of the first stage and to connect an output terminal of the shift register unit of the first stage with the input terminal of the shift register unit of the second stage;
• a third switching unit configured to be turned on in response to a first signal and to connect a first node with the input terminal of the shift register unit of the second stage;
• a fourth switching unit configured to be turned on in response to the gate drive signal and to connect the first node with an input terminal of the shift register unit of the first stage;
• a fifth switching unit configured to be turned on in response to the gate drive signal and to transmit the gate drive signal with a reset terminal of the shift register unit of the N−1th stage;
• a sixth switching unit configured to be turned on in response to an output signal of the shift register unit of the Nth stage and to connect an output terminal of the shift register unit of the Nth stage with the reset terminal of the shift register unit of the N−1th stage;
• a seventh switching unit configured to be turned on in response to a second signal and to connect a second node to the reset terminal of the shift register unit of the N−1th stage;
• an eighth switching unit configured to be turned on in response to the gate drive signal and to connect a reset terminal of the shift register unit of the Nth stage with the second node;
• wherein the driving method comprises:
• performing a forward scan, where the first switching unit is turned on by the gate drive signal, to transmit the gate drive signal to the input terminal of the shift register unit of the second stage, so that the shift register circuit starts performing the forward scan from the shift register unit of the second stage, and at the same time, the fifth switching unit and the eighth switching unit are turned on by the gate drive signal, and the seventh switching unit is turned on by the second signal, to transmit the gate drive signal to the reset terminal of the shift register unit of the Nth stage and the reset terminal of the shift register unit of the N−1th stage, when scanning to the shift register unit of the Nth stage, the sixth switching unit is turned on by the output signal of the shift register unit of the Nth stage, to transmit the output signal to the reset terminal of the shift register unit of the N−1th stage;
• and
• switching the forward scan to a reverse scan, where the first signal and the second signal are interchanged to interchange the reset terminals and the input terminals of the shift register units, and switch the first clock signal and the second clock signal, the fifth switching unit is turned on by the gate drive signal, to transmit the gate drive signal to the input terminal of the shift register unit of the N−1th stage, so that the shift register circuit starts performing the reverse scan from the shift register unit of the N−1th stage, and at the same time, the first switching unit and the fourth switching unit are turned on by the gate drive signal, the third switching unit is turned on by the first signal, to transmit the gate drive signal to the reset terminal of the shift register unit of the first stage and the reset terminal of the shift register unit of the second stage, when scanning to the shift register unit of the first stage, the second switching unit is turned on by the output signal of the shift register unit of the first stage, to transmit the output signal to the reset terminal of the shift register unit of the second stage.