Memory arrays and methods of forming the same

A method of operating a device, the device comprising at least one memory cell over a substrate, the memory cell having a source region and a drain region in the substrate, a first gate and a second gate over the substrate, wherein the first gate and the second gate are arranged between the source region and the drain region, wherein the first gate is arranged between the drain region and the second gate, wherein the first gate and the second gate are separated by an intergate dielectric, wherein the first gate is configured as a select gate and erase gate of the at least one memory cell, and the second gate is configured as a storage gate of the at least one memory cell, wherein the second gate comprises a floating gate and a control gate over the floating gate, wherein the floating gate is separated from the substrate by a tunneling dielectric, a second drain region in the substrate, wherein a third gate and a fourth gate are arranged between the source region and the second drain region, wherein the third gate is configured as a second select gate and second erase gate of the at least one memory cell, and the fourth gate is configured as a second storage gate of the at least one memory cell, wherein the fourth gate comprises a second floating gate and a second control gate over the second floating gate, source/drain (S/D) contacts extending from the source and drain regions, the source region and the drain region are coupled to either one of a source line (SL) and a bit line (BL) through the S/D contacts, the first gate is coupled to a wordline (WL) and the control gate is coupled to a control gate line (CG), the method comprising:

• applying biasing voltages to the SL, BL, CG, and WL to trigger electron tunneling from a channel in the substrate beneath the floating gate through the tunneling dielectric to the floating gate during programming operations, and electron tunneling from the floating gate through the intergate dielectric to the first gate during erase operations.

A method of forming a device, comprising:

• providing a substrate;
• and
• arranging at least one memory cell over the substrate, wherein arranging the at least one memory cell comprises:
• forming a source region and a drain region in the substrate, and
• arranging a first gate and a second gate over the substrate, wherein the first gate and the second gate are arranged between the source region and the drain region, wherein the first gate is arranged between the drain region and the second gate, wherein the first gate and the second gate are separated by an intergate dielectric, wherein the first gate is configured as a select gate and erase gate of the at least one memory cell, and the second gate is configured as a storage gate of the at least one memory cell, wherein the second gate comprises a floating gate and a control gate over the floating gate,
• forming a second drain region in the substrate and arranging a third gate and a fourth gate between the source region and the second drain region;
• wherein the third gate is configured as a second select gate and a second erase gate of the at least one memory cell, and the fourth gate is configured as a second storage gate of the at least one memory cell, wherein the fourth gate comprises a second floating gate and a second control gate over the second floating gate,
• forming source/drain (S/D) contacts over the source region and the drain region, wherein the source region and the drain region are coupled to either one of a source line (SL) and a bit line (BL) through the S/D contacts.