Semiconductor memory device

A semiconductor memory device comprising:

• a first power supply pad to which a high-side power supply voltage is supplied from an exterior of the semiconductor memory device;
• a plurality of second power supply pads to each of which a low-side power supply voltage is supplied from the exterior of the semiconductor memory device;
• a first plane including
• a first memory cell array including a plurality of first blocks, the first blocks having a first common source line, one of the first blocks including a first memory cell,
• a first row decoder disposed on both sides in a first direction of the first memory cell array, and electrically connected to the first blocks via a plurality of first word lines,
• a first sense amplifier disposed on one side in a second direction of the first memory cell array, and electrically connected to the first blocks via a plurality of first bit lines, the second direction crossing the first direction,
• a first voltage generator disposed on the one side in the second direction of the first sense amplifier, and configured to generate voltages, and
• a first source line driver disposed between the first memory cell array and the first sense amplifier in the second direction, electrically connected to the first voltage generator, and configured to control a voltage of the first common source line, the first source line driver including
• a first transistor having one end electrically connected to the first common source line, and
• a first comparison circuit having one input node connected to the first common source line, the other input node supplied with a first reference voltage, and an output node electrically connected to a gate of the first transistor;
• a second plane disposed on one side in the first direction of the first plane and including
• a second memory cell array including a plurality of second blocks, the second blocks having a second common source line, one of the second blocks including a second memory cell;
• a second row decoder disposed on the both sides in the first direction of the second memory cell array, and electrically connected to the second blocks via a plurality of second word lines,
• a second sense amplifier disposed on the one side in the second direction of the second memory cell array, and electrically connected to the second blocks via a plurality of second bit lines,
• a second voltage generator disposed on the one side in the second direction of the second sense amplifier, and configured to generate voltages, and
• a second source line driver disposed between the second memory cell array and the second sense amplifier in the second direction, electrically connected to the second voltage generator, and configured to control a voltage of the second common source line, the second source line driver including
• a second transistor having one end electrically connected to the second common source line, and
• a second comparison circuit having one input node connected to the second common source line, the other input node supplied with a second reference voltage, and an output node electrically connected to a gate of the second transistor;
• a first wiring that electrically connects the other end of the first transistor and one of the second power voltage supply pads;
• and
• a second wiring that is different from and does not come into electrical contact with the first wiring and that electrically connects the other end of the second transistor and another one of the second power voltage supply pads.