Resistive random access memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
Life of this patent
Estimating the term…
Abstract
A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
Claims20
A memory architecture, comprising:
- a plurality of cell arrays comprising
- a first cell array comprising a first plurality of bit cells using a first variable resistance dielectric layer to transition between logic states,
- a second cell array comprising a second plurality of bit cells using a second variable resistance dielectric layer to transition between logic states, and
- a third cell array comprising a third plurality of bit cells using a third variable resistance dielectric layer to transition between logic states;
- and
- a control logic circuit, coupled to the plurality of cell arrays, and configured to
- cause a first information bit to be written into respective bit cells of the first and second cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, and
- cause a second information bit to be written into a single bit cell of the third cell array as an original logic state of the second information bit,
- wherein
- the first, second, and third variable resistance dielectric layers are formed based on a same recipe of deposition equipment,
- each of the first and second variable resistance dielectric layers has a first diameter, and
- the third variable resistance dielectric layer has a second diameter that is different from the first diameter.
A memory architecture, comprising:
- a first cell array comprising a first plurality of bit cells;
- a second cell array comprising a second plurality of bit cells;
- a third cell array comprising a third plurality of bit cells;
- and
- a control logic circuit, coupled to the first, second, and third cell arrays, and configured to cause a first information bit to be written into respective bit cells of the first and second cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, and a second information bit into a bit cell of the third cell array as an original logic state of the second information bit, such that the respective bit cells of the first and second cell arrays have a first endurance and the bit cell of the third cell array has a second endurance,
- wherein the first endurance comprises a maximum number of cycles for which the respective bit cells of the first and second cell arrays can transition between respective different resistance states, and the second endurance comprises a maximum number of cycles for which the bit cell of the third cell array can transition between respective different resistance states.
A method, comprising:
- providing a memory architecture comprising a plurality of memory cell arrays, wherein respective memory cells of the plurality of memory cell arrays share a universal variable resistance dielectric layer;
- selecting first and second memory cell arrays of the plurality of memory cell arrays to be used in a first application with a first endurance;
- selecting a third memory cell array of the plurality of memory cell arrays to be used in a second application with a second endurance;
- writing a first information bit into respective memory cells of the first and second memory cell arrays as the first information bit's original and complementary logic states;
- and
- writing a second information bit into a memory cell of the third memory cell array as the second information bit's original logic state,
- wherein the first endurance comprises a maximum number of cycles for which the respective memory cells of the first and second cell arrays can transition between respective different resistance states, and the second endurance comprises a maximum number of cycles for which the memory cell of the third cell array can transition between respective different resistance states.
Dependencies are inferred from the claim text.