Writing multiple levels in a phase change memory

A phase change memory system comprising a read head which includes a sense comparator having multiple inputs and an output,

• wherein:
• the sense comparator is configured to change logic states from a high logic state to a low logic state when a first input and a second input which is connected to a storage cell are a same value or substantially the same value,
• the storage cell is associated with a bit line, a word line, a master bit line and a column decoder,
• the column decoder selectively connects the storage cell and the bit line to the master bit line via transistor, and
• the storage cell is selected for reading by the bit line, the word line and the column decoder such that a voltage corresponding to a value of the storage cell is produced on the master bit line.