Resistive memory device including a reference cell and method of controlling a reference cell to identify values stored in memory cells

A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells, the method comprising:

• writing a first value to the plurality of memory cells;
• setting monotonically increasing or monotonically decreasing resistances of a reference resistor through which a reference current passes, wherein the reference current also passes through the reference cell, and wherein the reference cell is a shorted cell;
• reading repeatedly the plurality of memory cells written as the first value, while the resistances of the reference resistor monotonically increase or decrease;
• and
• determining a read reference resistance, based on an aggregation of results of the repeated reading by estimating a first distribution of resistances corresponding to the first value stored in the memory cells based on the results of the repeated reading.

A resistive memory device configured to receive a reference adjustment signal, the resistive memory device comprising:

• a cell array comprising memory cells and a reference cell, wherein the memory cells are connected to respective first source lines and respective first bit lines, and wherein the reference cell is connected to a second source line and a second bit line;
• a current source circuit configured to provide, in response to a read command, a read current and a variable reference current respectively to the memory cells and the reference cell via the first source lines or the second source line;
• an amplification circuit configured to detect voltages between the first source lines connected to the memory cells and the second source line connected to the reference cell;
• and
• a control circuit configured to control the current source circuit such that the reference current is adjusted regardless of the read current, in response to the reference adjustment signal,
• wherein the reference cell comprises:
• a transistor connected to the second source line and the second bit line and having a gate connected to a word line that is connected to at least one of the memory cells,
• wherein the transistor is configured to electrically connect the second source line and the second bit line in response to the word line being activated, and
• wherein a memory cell of the memory cells comprises a magnetic tunnel junction (MTJ) element and a transistor serially connected between a corresponding third source line of the first source lines and a corresponding third bit line of the first bit lines connected to the memory cell, and
• wherein the transistor comprises a gate connected to a same word line as the reference cell.