Memory array with reduced circuitry
AssigneeInternational Business Machines Corporation
InventorsNoam Jungmann, Donald W. Plass
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Abstract
A memory array is described herein that includes a static random-access memory (SRAM) array to store data. The memory array also includes a bit circuit to retrieve the data from the SRAM array, the bit circuit to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state. Furthermore, the memory array includes a sense amplifier to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor.
Claims20
A memory array comprising:
- a static random-access memory (SRAM) array to store data;
- a bit circuit to retrieve the data from the SRAM array, the bit circuit is coupled to a plurality of bit lines to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state;
- and
- a sense amplifier to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor (PFET).
A method for manufacturing a memory array comprising:
- manufacturing the memory array to include a static random-access memory (SRAM) array to store data;
- manufacturing the memory array to further include a bit circuit to retrieve the data from the SRAM array, the bit circuit is coupled to a plurality of bit lines to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state;
- and
- manufacturing the memory array to further include a sense amplifier to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor (PFET).
A computer program product for designing a memory chip, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions being executable by a processor to cause the processor to:
- design the memory chip comprising a static random-access memory (SRAM) array to store data;
- add a bit circuit to the memory chip to retrieve the data from the SRAM array, the bit circuit is coupled to a plurality of bit lines to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state;
- and
- add a sense amplifier to the memory chip to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor (PFET).
Dependencies are inferred from the claim text.