Static random access memory device with keeper circuit

A static random-access memory (SRAM) device, comprising:

• a plurality of bit line groups each including a first bit line and a second bit line disposed in parallel;
• a first word line perpendicular to the first bit line and the second bit line of each bit line group;
• a second word line parallel to the first word line;
• a plurality of first memory cells respectively coupled to a corresponding bit line group among the plurality of bit line groups, and coupled to the first word line;
• a plurality of second memory cells respectively coupled to a corresponding bit line group among the plurality of bit line groups, and coupled to the second word line;
• a first keeper circuit and a first strapping cell disposed between the plurality of first memory cells and a logic circuit, and coupled to the first bit line and the second bit line of each bit line group;
• a second keeper circuit and a second strapping cell disposed between the plurality of first memory cells and the plurality second memory cells;
• and
• a third keeper circuit disposed between the plurality of first memory cells and the plurality second memory cells, wherein the second strapping cell is disposed between the second keeper circuit and the third keeper circuit.