Buffer control circuit of memory device
AssigneeSK hynix Inc.
InventorsKyung-Mook Kim, Sang-Ah Hyun
Life of this patent
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Abstract
A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N−1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N−1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.
Claims22
A memory device comprising:
- a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio;
- a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock;
- a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N−1)th current control signals;
- and
- a buffer circuit suitable for adjusting an amount of current based on the first to (N−1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.
A memory system comprising:
- a plurality of memory devices;
- and
- a memory controller suitable for transferring and receiving data to and from the memory devices and providing a command/address signal, a clock enable signal, a global reset signal and an external clock to control the memory devices,
- wherein each of the memory devices includes:
- a clock buffer circuit suitable for receiving the external clock based on the clock enable signal to output an internal clock;
- a buffer control circuit suitable for generating a current control signal corresponding to a frequency of the internal clock during a standby period defined by the clock enable signal and the global reset signal;
- and
- a buffer circuit suitable for adjusting an amount of current based on the current control signal and buffering the command/address signal, the clock enable signal, the global reset signal and the data using the adjusted amount of current.
A buffer circuit comprising:
- a differential amplification block suitable for receiving an externally inputted signal and a reference voltage;
- a current amount adjustment block suitable for adjusting an amount of current used for receiving the reference voltage based on a current control signal;
- and
- a buffer control circuit suitable for generating the current control signal corresponding to a frequency of a system clock during a standby period.
Dependencies are inferred from the claim text.