Floating body DRAM with reduced access energy

A method of operation in an integrated circuit (IC) memory device, the method comprising:

• receiving read transaction component signals for accessing a first group of floating body dynamic random access memory (FBDRAM) storage cells, the read transaction component signals issued from an external memory controller and including an activate command and a read command;
• sensing data stored in the accessed first group of the FBDRAM storage cells as sensed data via sensing circuitry;
• and
• conditionally performing a writeback operation of the sensed data associated with the read command in response to a writeback command generated by conditional writeback circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a first sense characteristic.

A memory comprising:

• memory control circuitry to issue a read command;
• and
• a memory device coupled to the memory control circuitry, the memory device including
• storage cells, each storage cell formed with a metal-oxide-semiconductor (MOS) transistor having a floating body, wherein data is stored as charge in the floating body;
• a transfer interface to receive a read command to access first data stored in a first group of the storage cells;
• sensing circuitry to detect the first data stored in the first group of the storage cells;
• and
• wherein the transfer interface conditionally performs a writeback operation associated with the read command in response to a writeback command generated by conditional writeback circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a sense characteristic.