# US 10,762,946 B2 · Memory with partial array refresh

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- Number: US 10,762,946 B2
- Document ID: US10762946B2
- Status: Granted
- Kind: B2
- Application number: 16/237,013
- Filed: 2018-12-31
- Published: 2020-07-02
- Granted: 2020-09-01
- Earliest claimed: 2018-12-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dale H. Hiscock; Debra M. Bell; Michael Kaminski; Joshua E. Alzheimer; Anthony D. Veches; James S. Rehmeyer
- Web page: https://patentgrep.com/patent/US10762946B2

## CPC

- G11C 11/40622: {Partial refresh of memory arrays}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 16/10: Programming or data input circuits
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 2211/406: Refreshing of dynamic cells
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

## Claims

### Claim 1

A memory device, comprising:
a memory array including a plurality of memory cells arranged in a plurality of memory regions, wherein the plurality of memory regions includes a first memory region and a second memory region; and
inhibit circuitry configured, during refresh operations of the memory device, to disable the second memory region of the plurality of memory regions from receiving refresh commands such that memory cells of the second memory region are not refreshed,
wherein, before writing data to unutilized memory cells of the second memory region, the memory device is configured to write data to unutilized memory cells of the first memory region until a threshold number of memory cells of the first memory region are utilized.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the inhibit circuitry is configured to disable the second memory region from receiving the refresh commands by masking the second memory region from the refresh commands.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the inhibit circuitry is further configured to toggle a reset pin of the second memory region when disabling the second memory region from receiving the refresh commands.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the inhibit circuitry is configured to disable the second memory region from receiving the refresh commands upon powering on the memory device or in response to a loss of power to the memory device.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the inhibit circuitry is configured to disable the second memory region from receiving the refresh commands when none of the memory cells of the second memory region contain valid, non-stale data.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first memory region is a memory bank.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the memory bank is a first memory bank in the memory array and/or a first memory bank in a memory bank group of the memory array.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the first memory region is a logical memory rank or die.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the inhibit circuitry is further configured to enable the second memory region to receive the refresh commands such that the memory cells of the second memory region are refreshed during the refresh operations in response to the second memory region receiving an activate command.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the memory device is further configured to write data to the memory cells of the second memory region when the threshold number of the memory cells of the first memory region are utilized.

### Claim 11

A method for refreshing data stored in a memory array of a memory device, the method comprising:
writing data to memory cells of the memory array in accordance with a programming sequence, wherein the programming sequence directs writing of data to memory cells of a first memory region in a plurality of memory regions of the memory array before writing data to unutilized memory cells of a second memory region in the plurality of memory regions until a threshold number of the memory cells first memory region are utilized; and
during refresh operations of the memory device, disabling the second memory region from receiving refresh commands such that memory cells of the second memory region are not refreshed.

### Claim 12 (depends on 11)

The method of claim 11, wherein the disabling includes masking the second memory region from the refresh commands and/or toggling a reset pin of the second memory region.

### Claim 13 (depends on 11)

The method of claim 11, wherein the disabling includes disabling the second memory region from receiving the refresh commands upon powering on the memory device or in response to a loss of power to the memory device.

### Claim 14 (depends on 11)

The method of claim 11, wherein the disabling includes disabling the second memory region from receiving the refresh commands when less than a threshold number of the memory cells of the second memory region are utilized.

### Claim 15 (depends on 11)

The method of claim 11, further comprising enabling the second memory region to receive the refresh commands such that the memory cells of the second memory region are refreshed during the refresh operations in response to the second memory region receiving an activate command.

### Claim 16

A memory system, comprising:
a memory controller;
a memory device operably connected to the memory controller,
wherein the memory device includes a memory array having a plurality of memory cells arranged in a plurality of memory regions,
wherein the plurality of memory regions includes a first memory region and a second memory region, and
wherein the memory controller is configured to track memory regions that include utilized memory cells; and
inhibit circuitry configured, during refresh operations of the memory device, to disable the second memory region from receiving refresh commands such that memory cells of the second memory region are not refreshed,
wherein, before writing data to unutilized memory cells of the second memory region, the memory system is configured to write data to unutilized memory cells of the first memory region until a threshold number of memory cells of the first memory region are utilized.

### Claim 17 (depends on 16)

The memory system of claim 16, wherein the inhibit circuitry is configured to disable the second memory region from receiving refresh commands by masking the second memory region from the refresh commands.

### Claim 18 (depends on 16)

The memory system of claim 16, wherein the inhibit circuitry is configured to disable the second memory region when none of the memory cells of the second memory region contain valid, non-stale data.

### Claim 19 (depends on 16)

The memory system of claim 16, wherein the memory system is further configured to write data to the memory cells of the first memory region after writing data to the memory cells of the second memory region only when the second memory region becomes more active than the first memory region.

### Claim 20 (depends on 16)

The memory system of claim 16, wherein the inhibit circuitry is further configured to enable the second memory region to receive the refresh commands such that the memory cells of the second memory region are refreshed during the refresh operations when a threshold number of the memory cells of the second memory region are utilized.

### Claim 21 (depends on 20)

The memory system of claim 20, wherein the threshold number of the memory cells of the second memory region is one.

### Claim 22 (depends on 16)

The memory system of claim 16, wherein the inhibit circuitry is further configured to enable the second memory region to receive the refresh commands such that the memory cells of the second memory region are refreshed during the refresh operations in response to the second memory region receiving an activate command.

### Claim 23 (depends on 16)

The memory system of claim 16, wherein the inhibit circuitry is configured to disable the second memory region from receiving the refresh commands in response to a power loss event of the memory device.

### Claim 24 (depends on 16)

The memory system of claim 16, wherein the first memory region is a memory bank or a logical memory rank or die of the memory array.

### Claim 25 (depends on 16)

The memory system of claim 16, wherein the memory system is further configured to write data to the memory cells of the second memory region when the threshold number of the memory cells of the first memory region are utilized.