Single plate configuration and memory array operation

An apparatus, comprising:

• an array of ferroelectric memory cells comprising a first ferroelectric memory cell and a second ferroelectric memory cell different than the first ferroelectric memory cell, wherein the first ferroelectric memory cell comprises a first switching component;
• a plate coupled with the first ferroelectric memory cell and the second ferroelectric memory cell;
• a word line coupled with the first ferroelectric memory cell and the second ferroelectric memory cell;
• a first digit line coupled with the first ferroelectric memory cell;
• a second switching component coupled with the first digit line and the plate, wherein the second switching component is configured to couple the first digit line and the plate, and wherein the first digit line and the plate are configured to operate at a same fixed voltage level throughout a memory access operation of the second ferroelectric memory cell based at least in part on coupling the first digit line and the plate;
• a second digit line different than the first digit line coupled with the second ferroelectric memory cell, wherein the second digit line is configured to operate at a voltage level different than the same fixed voltage level during the memory access operation of the second ferroelectric memory cell;
• and
• a third switching component coupled with the first digit line and the second digit line, wherein the third switching component is configured to isolate the first digit line from the second digit line.

An apparatus, comprising:

• an array of ferroelectric memory cells having a first ferroelectric memory cell and a second ferroelectric memory cell, wherein the first ferroelectric memory cell comprises a first switching component;
• a first digit line coupled with the first ferroelectric memory cell;
• a second digit line coupled with the second ferroelectric memory cell;
• a word line coupled with the first ferroelectric memory cell and the second ferroelectric memory cell;
• a plate line coupled with the first ferroelectric memory cell, the second ferroelectric memory cell, the first digit line, and the second digit line;
• a second switching component coupled with the first digit line and the plate line;
• a third switching component coupled with the first digit line and the second digit line;
• and
• a memory controller coupled with at least one memory cell of the array of ferroelectric memory cells, the memory controller operable to:
• apply, throughout an access operation of the second ferroelectric memory cell, a first voltage to the plate line;
• activate, throughout the access operation, the second switching component, wherein the first voltage is applied to the first digit line based at least in part on activating the second switching component;
• apply a second voltage to the word line to select the second ferroelectric memory cell;
• apply a third voltage to the second digit line to access the second ferroelectric memory cell, wherein the second digit line is isolated from the first digit line by the third switching component;
• reduce the second voltage to a fourth voltage that is lower than the second voltage during the access operation of the second ferroelectric memory cell and after the second voltage and the third voltage are applied;
• and
• reduce the fourth voltage applied to the word line to a fifth voltage after a completion of the access operation.

An apparatus, comprising:

• an array of ferroelectric memory cells having a first ferroelectric memory cell coupled with a first digit line and having a second ferroelectric memory cell coupled with a second digit line;
• a plate coupled with the first ferroelectric memory cell and the second ferroelectric memory cell;
• and
• a latch coupled with the second ferroelectric memory cell;
• a driver coupled with the second ferroelectric memory cell through the second digit line, the driver comprising:
• a first transistor;
• and
• a precharge voltage selector coupled with the first transistor and the latch, wherein the precharge voltage selector is configured to apply, after a writeback operation for the second ferroelectric memory cell, a negative voltage to the second digit line through the first transistor based at least in part on a logic state stored by the latch.