Semiconductor device
AssigneeSK hynix Inc.
InventorsJae Hwan Seo, Sung Soo Chi
Life of this patent
Estimating the term…
Abstract
A semiconductor device is disclosed. The semiconductor device includes a first cell array and a second cell array, a first main word line disposed over the first cell array, a second main word line disposed over the second cell array, and a row decoder block disposed between the first cell array and the second cell array, and configured to include a common signal line that is commonly coupled to the first main word line and the second main word line such that a main word line control signal is simultaneously supplied to the first main word line and the second main word line.
Claims20
A semiconductor device comprising:
- a first bank and a second bank, each of which includes a plurality of cell arrays;
- a first main word line disposed over the first bank;
- a second main word line disposed over the second bank;
- and
- a row decoder block disposed between the first bank and the second bank,
- wherein the row decoder block includes
- a unit row decoder configured to output a main word line control signal based on a row address;
- a common signal line formed in a line type that extends in a first direction over the unit row decoder, and configured to simultaneously transmit the main word line control signal to the first main word line and the second main word line;
- and
- a plurality of power lines configured to supply a power-supply voltage to the unit row decoder, and located in the same layer as in the common signal line.
A semiconductor device comprising:
- a first bank and a second bank, each of which includes a plurality of cell arrays;
- a plurality of first main word lines disposed over the first bank;
- a plurality of second main word lines disposed over the second bank;
- and
- a row decoder block disposed between the first bank and the second bank, and configured to include multiple common signal lines that are commonly coupled to the first main word lines and the second main word lines disposed in the same row such that a main word line control signal is simultaneously supplied to a corresponding first main word line and a corresponding second main word line,
- wherein the row decoder block includes a plurality of power lines located in the same layer as in the common signal lines.
A semiconductor device comprising:
- a first cell array and a second cell array;
- a first main word line disposed over the first cell array;
- a second main word line disposed over the second cell array;
- and
- a row decoder block disposed between the first cell array and the second cell array, and configured to include a common signal line that is commonly coupled to the first main word line and the second main word line such that a main word line control signal is simultaneously supplied to the first main word line and the second main word line,
- wherein the row decoder block includes a plurality of power lines located in the same layer as in the common signal line.
Dependencies are inferred from the claim text.