Semiconductor device and memory system

A semiconductor device comprising:

• a first input circuit in which, between a first transistor with a first conductivity type and a first transistor with a second conductivity type, a second transistor with the first conductivity type and a second transistor with the second conductivity type are arranged, the second transistor with the first conductivity type and the second transistor with the second conductivity type having gates commonly connected to a second input node, the first transistor with the first conductivity type and the first transistor with the second conductivity type having gates commonly connected to a first input node;
• a first latch circuit in which a connection of a fourth transistor with the first conductivity type and a fourth transistor with the second conductivity type and a connection of a fifth transistor with the first conductivity type and a fifth transistor with the second conductivity type are arranged in parallel between a third transistor with the first conductivity type and a third transistor with the second conductivity type, the fourth transistor with the first conductivity type and the fourth transistor with the second conductivity type having gates commonly connected to the first input node and having drains commonly connected to a first node, the fifth transistor with the first conductivity type and the fifth transistor with the second conductivity type having gates commonly connected to the second input node and having drains commonly connected to the first node, the third transistor with the first conductivity type and the third transistor with the second conductivity type having gates commonly connected to a second node connected to the first node on an output side of the first input circuit via a first inverter;
• a first pull-up circuit connected to a third node, and to a fourth node, the third node being a node between a drain of the first transistor with the first conductivity type and a source of the second transistor with the first conductivity type in the first input circuit, the fourth node being a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type in the first latch circuit;
• and
• a first pull-down circuit connected to a fifth node, and to a sixth node, the fifth node being a node between a drain of the first transistor with the second conductivity type and a source of the second transistor with the second conductivity type in the first input circuit, the sixth node being a node between a drain of the third transistor with the second conductivity type, and a source of the fourth transistor with the second conductivity type and a source of the fifth transistor with the second conductivity type the first latch circuit.