Semiconductor devices
AssigneeSK hynix Inc.
InventorsMyung Kyun Kwak, Woongrae Kim, Seung Hun Lee
Life of this patent
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Abstract
A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.
Claims23
A semiconductor device comprising:
- a burst end signal generation circuit configured to generate a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and configured to generate the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode;
- and
- an auto-pre-charge control circuit configured to perform an auto-pre-charge operation based on the write burst end signal,
- wherein the internal write flag is generated by shifting the write flag by a period determined based on a shift control signal,
- wherein the internal latched burst mode signal is generated by shifting the latched burst mode signal by a period determined based on the shift control signal, and
- wherein the shift control signal is generated based on a frequency ratio of a data clock signal to an internal clock signal.
A semiconductor device comprising:
- a flag shift circuit configured to shift a write flag by a period determined based on a shift control signal to generate an internal write flag;
- a burst mode signal latch circuit configured to latch a burst mode signal based on an input control signal and configured to output the latched signal of the burst mode signal as a latched burst mode signal based on an output control signal;
- a burst mode signal shift circuit configured to shift the latched burst mode signal by a period determined based on the shift control signal to generate an internal latched burst mode signal;
- and
- a burst end signal generation circuit configured to generate a write burst end signal based on the write flag and the latched burst mode signal in a first burst mode and configured to generate the write burst end signal based on the internal write flag and the internal latched burst mode signal in a second burst mode, wherein the shift control signal is generated based on a bank mode for a write operation and information on a burst length.
A semiconductor device comprising:
- a flag shift circuit configured to shift a read flag by a period determined based on a shift control signal to generate an internal read flag;
- a burst mode signal shift circuit configured to shift a burst mode signal by a period determined based on the shift control signal to generate an internal burst mode signal;
- and
- a burst end signal generation circuit configured to generate a read burst end signal based on the read flag and the burst mode signal in a first burst mode and configured to generate the read burst end signal based on the internal read flag and the internal burst mode signal in a second burst mode, wherein the shift control signal is generated based on a bank mode for a read operation and information on a burst length.
Dependencies are inferred from the claim text.