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US 10,762,932 B2Granted
Memory device and operating method of memory device
AssigneeSamsung Electronics Co., Ltd.
InventorArtur Antonyan
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.
Claims20
A magnetic random access memory device comprising:
- a memory cell array comprising a plurality of memory cells, each of the plurality of memory cells comprising a magnetic memory cell;
- a row decoder connected to the memory cell array through a plurality of word lines;
- a column decoder connected to the memory cell array through a plurality of bit lines and a plurality of source lines;
- a write driver configured to generate a write voltage to a bit line of the plurality of bit lines, wherein the bit line is selected by the column decoder, from among the plurality of bit lines by using a gate voltage in a write operation;
- and
- control logic configured to generate the gate voltage,
- wherein the gate voltage is higher than the write voltage,
- wherein the magnetic memory cell comprises:
- a variable resistance element a first state having a first resistance value and a second state having a second resistance value, the variable resistance element comprising:
- a free layer having variable magnetization direction and connected to a corresponding bit line among the plurality of bit lines;
- a pinned layer having a fixed magnetization direction;
- and
- a tunneling layer between the free layer and the pinned layer;
- and
- a selection transistor comprising:
- a gate connected to a corresponding word line among the plurality of word lines;
- a first terminal connected to a corresponding source line among the plurality of source lines;
- and
- a second terminal connected to the variable resistance element.
16 more elements
A magnetic random access memory device comprising:
- a memory cell array comprising a plurality of memory cells, each of the plurality of memory cells comprising a magnetic memory cell;
- a row decoder connected to the memory cell array through a plurality of word lines;
- a column decoder connected to the memory cell array through a plurality of bit lines and/or a plurality of source lines;
- a write driver configured to generate a write voltage to a bit line of the plurality of bit lines, which is selected by the column decoder, from among the plurality of bit lines by using a gate voltage in a write operation;
- and
- control logic configured to generate the gate voltage,
- wherein the control logic comprises:
- a reference resistance element connected between a comparison node and a ground node;
- a transmission gate connected to the comparison node and configured to operate in response to first and second enable signals;
- a gate transistor connected between a power node and the transmission gate and configured to operate in response to the gate voltage;
- a comparator configured to compare a reference voltage and a comparison voltage of the comparison node and output a third enable signal in response to a result of the compare;
- and
- a charge pump configured to generate the gate voltage in response to the third enable signal.
10 more elements
A method of operating a magnetic random access memory device comprising magnetic memory cells, the method comprising:
- adjusting a reference voltage;
- adjusting a resistance value of a reference resistance element from a first resistance value to a second resistance value;
- adjusting a capacity of a charge pump from a first capacity to a second capacity;
- comparing a comparison voltage generated by the reference resistance element having the second resistance value with the reference voltage;
- activating or deactivating the charge pump having the second capacity based on a result of the comparing, in order to adjust a gate voltage from a first gate voltage to a second gate voltage;
- and
- supplying a write voltage to one or more of the magnetic memory cells responsive the second gate voltage.
4 more elements
Dependencies are inferred from the claim text.