Memory power management
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSanjeev Kumar Jain, Jaspal Singh Shah
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
Claims20
A memory device comprising:
- a plurality of arrays of memory cells;
- a plurality of peripheral circuits operably coupled to the plurality of arrays of memory cells;
- a plurality of voltage terminals corresponding to the plurality of arrays of memory cells and the plurality of peripheral circuits;
- a power control circuit configured to individually control an electrical connection of each of the plurality of peripheral circuits and the plurality of arrays of memory cells to their corresponding voltage terminals;
- a plurality of sensors configured to detect the electrical connection of each of the plurality of peripheral circuits and the plurality of arrays array of memory cells to their corresponding voltage terminals;
- and
- an isolation circuit configured to electrically isolate adjacent peripheral circuits from one another.
The memory device of the 9, further comprising a plurality of isolation circuits configured to electrically isolate the plurality of peripheral circuits from another.
A memory power control system, comprising:
- a power controller including:
- a first output terminal configured to provide a first power control signal to selectively electrically connect a first memory array of a memory device to a corresponding voltage terminal;
- a second output terminal configured to provide a second power control signal to selectively connect a second memory array of the memory device to a corresponding voltage terminal;
- a third output terminal configured to provide a third power control signal to selectively connect a first peripheral circuit of the memory device to a corresponding voltage terminal;
- a fourth output terminal configured to provide a fourth power control signal to selectively connect a second peripheral circuit of the memory device to a corresponding voltage terminal;
- and
- an isolation circuit configured to selectively electrically isolate the first peripheral circuit from the second peripheral circuit.
A memory device power control method, comprising:
- providing a memory device including a plurality of memory arrays each having a plurality of memory cells, a first peripheral circuit and a second peripheral circuit;
- operating the memory device in a first power management mode including removing power from the first and second peripheral circuits;
- operating the memory device in a second power management mode including applying power to the first peripheral circuit and removing power from the second peripheral circuit;
- and
- selectively interrupting a current path between the first peripheral circuit and the second peripheral circuit.
Dependencies are inferred from the claim text.