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US 10,762,930 B2Granted
Semiconductor device with memory banks and sense amplifier arrays
AssigneeSK hynix Inc.
InventorsHyung Sik Won, Seung Han Oak, Jun Phyo Lee
Life of this patent
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Abstract
A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.
Claims18
A semiconductor device comprising:
- a plurality of memory banks arranged in a first direction;
- an address decoder arranged at one side of the memory banks;
- a plurality of local sense amplifier arrays, a corresponding one of which is arranged under each of the memory banks;
- a plurality of first input/output lines, a corresponding one of which is connected between a corresponding memory bank and its associated local sense amplifier array;
- and
- at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction,
- wherein each of the memory banks comprises:
- a plurality of MATs arranged in the first direction, the MATs including a plurality of memory cells;
- a plurality of normal sense amplifier arrays arranged between the MATs;
- and
- a plurality of edge sense amplifier arrays arranged on an uppermost MAT and a lowermost MAT among the MATs.
8 more elements
A semiconductor device comprising:
- a plurality of memory banks;
- and
- a plurality of local sense amplifier arrays, a corresponding one of which is arranged under each of the memory banks;
- wherein each of the plurality of memory banks includes:
- a plurality of MATs including a plurality of memory cells, the MATs adjacent to each other in a first direction;
- a plurality of sense amplifier arrays arranged between the MATs, each of the sense amplifier arrays including a plurality of sense amplifiers;
- edge sense amplifier arrays arranged over an uppermost MAT and under a lowermost MAT among the MATs;
- and
- a plurality of column selection signal lines extended on the first sense amplifier arrays in a second direction perpendicular to the first direction to transmit column selection signals to the first sense amplifiers.
6 more elements
Dependencies are inferred from the claim text.