Memory-in-pixel circuit and driving method thereof, liquid crystal display panel and wearable device

A memory-in-pixel circuit, comprising:

• a latch circuit, a switch circuit and a selection circuit, wherein all transistors included in the latch circuit merely are first type transistors, and the latch circuit is configured to latch a data voltage and generate a first latch signal and a second latch signal;
• a first end of the switch circuit is electrically connected with a data line to receive the data voltage, a control end of the switch circuit receives a row scan signal, and the second end of the switch circuit is electrically connected with the selection circuit, and the switch circuit is configured to provide the data voltage to an input end of the latch circuit upon the switch circuit being turned on;
• and a first input end of the selection circuit is electrically connected with a second output end of the latch circuit, a second input end of the selection circuit is electrically connected with a first output end of the latch circuit, a first control end of the selection circuit is configured to receive a first selection signal, and a second control end of the selection circuit is configured to receive a second selection signal, and the selection circuit is configured to apply the first latch signal or the second latch signal to a pixel under control of the first selection signal and the second selection signal, and to continue to apply the first latch signal or the second latch signal to the pixel upon the switch circuit being turned off, so as to achieve automatic update of the pixel, wherein the latch circuit comprises:
• a first latch transistor, a first electrode and a gate electrode of the first latch transistor being electrically connected with a first power supply terminal;
• a second latch transistor, a gate electrode of the second latch transistor being electrically connected with the first node, a first electrode of the second latch transistor being electrically connected with a second electrode of the first latch transistor so as to form a second node, and a second electrode of the second latch transistor being electrically connected with a second power supply terminal;
• a third latch transistor, both a first electrode and a gate electrode of the third latch transistor being electrically connected with the first power supply terminal;
• and a fourth latch transistor, a first electrode of the fourth latch transistor being electrically connected with a second electrode of the third latch transistor so as to form a third node, a gate electrode of the fourth latch transistor being electrically connected with the second node, a second electrode of the fourth latch transistor being electrically connected with the second power supply terminal, wherein the third node is further electrically connected with the first node, the input end of the latch circuit comprises the first node, the first output end of the latch circuit comprises the second node, and the second output end of the latch circuit comprises the third node.